Trench capacitor with warpage reduction
A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.
1. A trench capacitor, comprising:
a plurality of trenches in a doped semiconductor surface layer of a substrate;
a dielectric layer that lines a surface of the plurality of trenches, a first polysilicon layer located on the dielectric layer; and
a second polysilicon layer located on the first polysilicon layer, the second polysilicon layer filling the plurality of trenches,
wherein the second polysilicon layer has a higher doping level as compared to the first polysilicon layer.
2. The trench capacitor of claim 1 , wherein the first polysilicon layer has a highest doping concentration at an interface with the second polysilicon layer.
3. The trench capacitor of claim 1 , wherein the doped semiconductor surface layer is located over a bulk substrate material, further comprising a back side metal layer on side of the bulk substrate material opposite the doped semiconductor surface layer.
4. The trench capacitor of claim 1 , wherein the doped semiconductor surface layer comprises at least one epitaxial layer.
5. The trench capacitor of claim 1 , wherein the dielectric layer comprises a thermal oxide layer.
6. The trench capacitor of claim 5 , wherein the thermal oxide layer has a thickness in a range between about 10 nm and about 50 nm.
7. The trench capacitor of claim 1 , wherein the plurality of trenches have a depth in a range from about 10 μm to about 50 μm.
8. A packaged semiconductor device, comprising:
a die pad;
a first die comprising a power transistor on the die pad;
a second die comprising a trench capacitor on the die pad, the trench capacitor comprising a plurality of trenches formed in a semiconductor layer, each trench including:
a dielectric layer that lines a surface of the plurality of the trench;
a first polysilicon layer located on the dielectric layer; and
a second polysilicon layer that fills the trench,
wherein a first electrode contact is coupled to a first terminal of the power transistor and a second electrode contact is coupled to a second terminal of the power transistor.
9. The packaged semiconductor device of claim 8 , wherein the die pad is located in a Quad Flat No-lead (QFN) package.
10. The packaged semiconductor device of claim 8 , wherein semiconductor layer comprises at least one epitaxial layer located over a semiconductor substrate.
11. The packaged semiconductor device of claim 10 , further comprising a metallic layer located on a side of the semiconductor substrate opposite the semiconductor layer.
12. The packaged semiconductor device of claim 11 , wherein the metallic layer is an electrode of the trench capacitor.
13. The packaged semiconductor device of claim 8 , wherein each trench of the plurality of trenches has a depth in a range from about 10 μm to about 50 μm.
14. The packaged semiconductor device of claim 8 , further comprising a metal layer that electrically connects to the second polysilicon layer of each of the trenches.
15. The packaged semiconductor device of claim 8 , wherein the first polysilicon layer is undoped and the second polysilicon layer is doped.
16. The packaged semiconductor device of claim 8 , wherein the second polysilicon layer has a greater dopant concentration than does the first polysilicon.
17. A device, comprising:
a plurality of trenches in a semiconductor substrate;
a first polysilicon layer located within the plurality of trenches and over a top surface of the substrate, the first polysilicon layer being continuous between the plurality of trenches;
a plurality of second polysilicon layers, each second polysilicon layer filling a corresponding trench of the plurality of trenches; and
a back-side metal layer on a side of the substrate opposite the top surface,
wherein the second polysilicon layers each extend to a top surface of the first polysilicon layer.
18. The device of claim 17 , wherein the first continuous polysilicon layer has a higher doping concentration than the plurality of second polysilicon layers.
19. The device of claim 17 , further comprising a thermal oxide layer between the first polysilicon layer and the semiconductor substrate.