IP Library › Granted Patent US 11,271,073
Granted Patent B2
US 11,271,073 · App. 16/988,276 · Granted Mar 8, 2022

Semiconductor device and method for fabricating the same

Inventor: Seung Muk Kim (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H01L28/60H01L27/1085H01L27/10805
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Quick Facts
Patent No.
US 11,271,073
App. No.
16/988,276
Granted
Mar 8, 2022
Kind
B2
Abstract

A method for fabricating a semiconductor device includes: forming a lower array including a plurality of bottom electrodes over a semiconductor substrate, a supporter supporting the bottom electrodes, and a dielectric layer that is formed over the bottom electrodes and the supporter; forming a gap-fill layer covering side portions of the lower array and an upper portion of the lower array; forming a capping portion covering the upper portion of the lower array over the gap-fill layer; performing a pull-back process of the gap-fill layer to form a gap-fill electrode aligned with the capping portion; and forming a low-resistivity electrode over the gap-fill electrode.

Claims (37)

1. A method for fabricating a semiconductor device, comprising:

forming a lower array including a plurality of bottom electrodes over a semiconductor substrate, a supporter supporting the bottom electrodes, and a dielectric layer over the bottom electrodes and the supporter;

forming a gap-fill layer covering side portions of the lower array and an upper portion of the lower array;

forming a capping portion covering the upper portion of the lower array over the gap-fill layer;

performing a pull-back process of the gap-fill layer to form a gap-fill electrode aligned with the capping portion; and

forming a low-resistivity electrode over the gap-fill electrode,

wherein the forming of the low-resistivity electrode over the gap-fill electrode includes:

forming a low-resistivity layer covering the side portions of the lower array and the upper portion of the lower array over the semiconductor substrate including the gap-fill electrode; and

etching the low-resistivity layer to cover the side portions of the lower array and the upper portion of the lower array over the gap-fill electrode.

2. The method of claim 1 , wherein the gap-fill layer includes protrusions that cover the side portions of the lower array, and the protrusions are cut by the pull-back process.

3. The method of claim 1 , wherein the gap-fill electrode further includes:

thin supporter-side side portions covering an edge portion of the supporter; and

bottom electrode-side side portions that extend from the supporter-side side portions,

wherein the bottom electrode-side side portion are thicker than the supporter-side side portions.

4. The method of claim 1 , wherein the pull-back process includes

laterally etching the gap-fill layer by using the capping portion as an etch barrier.

5. The method of claim 1 , wherein the pull-back process includes a dry etching process or a wet dip-out process.

6. The method of claim 1 , wherein the gap-fill layer includes a semiconductor material.

7. The method of claim 1 , wherein the gap-fill layer includes a silicon layer, a boron-doped silicon layer, a silicon germanium layer, a boron-doped silicon germanium layer, a silicon carbide, or a combination thereof.

8. The method of claim 1 , wherein the capping portion includes a material having an etch selectivity with respect to the gap-fill layer.

9. The method of claim 1 , wherein the capping portion includes silicon oxide, silicon nitride, amorphous carbon or a photoresist.

10. The method of claim 1 , wherein the forming of the capping portion covering the upper portion of the lower array over the gap-fill layer includes:

forming a capping material that conformally covers the side portions of the lower array and the upper portion of the lower array over the gap-fill layer;

forming a mask layer that masks the upper portion of the lower array over the capping material; and

removing a portion of the capping material by using the mask layer as an etch barrier to form the capping portion over the lower array.

11. The method of claim 1 , further comprising:

cutting a portion of the gap-fill electrode to be aligned with the low-resistivity electrode, after the etching of the low-resistivity layer to cover the side portions of the lower array and the upper portion of the lower array over the gap-fill electrode.

12. The method of claim 1 , further comprising:

forming a contact plug that is physically spaced apart from the low-resistivity electrode in a region spaced apart from the lower array, after the forming of the low-resistivity electrode over the gap-fill electrode.

13. The method of claim 1 , wherein the gap-fill electrode includes:

a gap-fill electrode upper portion covering the upper portion of the lower array; and

gap-fill electrode side portions that extend from the gap-fill electrode upper portion to cover the side portions of the lower array,

wherein the gap-fill electrode side portions have a vertical profile.

14. The method of claim 13 , wherein the gap-fill electrode side portions are laterally retreated, compared with side portions of the gap-fill layer.

15. The method of claim 13 , wherein the gap-fill electrode further includes

a gap-fill electrode edge bottom portion that extends from the gap-fill electrode side portions,

wherein the gap-fill electrode edge bottom portion is laterally retreated, compared with an edge portion of the gap-fill layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2020
From: KIM, SEUNG MUK
To: SK HYNIX INC.
Reel/Frame 053436/0637 →
Priority Claims (1)
KR 10-2020-0025900 · Mar 2, 2020 · national
Continuity (1)
Related Publication 20210272959A1 · Sep 2, 2021
Cited By (1)
US 12,672,275