Analog-to-digital converter

1. An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits, comprising:

a plurality of sub-ADCs that are cascaded in a pipeline, wherein each sub-ADC of the plurality of sub-ADCs is configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits, and each sub-ADC of the plurality of sub-ADCs except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as an input signal to a succeeding sub-ADC in the pipeline, wherein at least one sub-ADC among the plurality of sub-ADCs is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits to be generated by each of the at least one sub-ADC while the input signal is sampled by each of the at least one sub-ADC;

a plurality of residue amplifiers, wherein each residue amplifier is coupled between two sub-ADCs and configured to amplify a residue signal output from a preceding sub-ADC in the pipeline and feed the amplified residue signal to a succeeding sub-ADC in the pipeline; and

a data synchronization circuitry configured to combine the digital bits output from the plurality of sub-ADCs to generate an ADC output.

2. The ADC of claim 1 , wherein each of the at least one sub-ADC includes a comparator configured to determine the MSB while the input signal is sampled.

3. The ADC of claim 1 , wherein the sub-ADCs are successive approximation register (SAR) ADCs.

4. The ADC of claim 1 , further comprising:

a sampler configured to sample the analog signal, wherein the sampled analog signal is fed to a first sub-ADC in the pipeline as the input signal to the first sub-ADC,

wherein the first sub-ADC includes a comparator configured to determine the MSB.

5. The ADC of claim 4 , further comprising:

a buffer configured to buffer the sampled analog signal and feed the sampled analog signal to the first sub-ADC in the pipeline as the input signal to the first sub-ADC.

6. The ADC of claim 1 , further comprising:

a first sampler configured to sample the analog signal; and

a second sampler configured to sample an output signal of the first sampler, wherein the sampled output signal of the first sampler is fed to a first sub-ADC in the pipeline as the input signal to the first sub-ADC,

wherein the first sub-ADC includes a comparator configured to determine the MSB.

7. The ADC of claim 6 , further comprising:

a buffer for buffing a signal between the first sampler and the second sampler or after the second sampler.

8. The ADC of claim 7 , wherein the buffer has a transfer function that is either amplification, attenuation, or gain of one.

9. The ADC of claim 1 , wherein the sub-ADCs are flash ADCs.

10. An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits, comprising:

a plurality of sub-ADCs that are arranged in parallel, wherein each of the plurality of sub-ADCs is configured to convert the analog signal to a pre-configured number of digital bits; and

at least one sampler configured to sample the analog signal and feed the sampled analog signal to the plurality of sub-ADCs, wherein the plurality of sub-ADCs are time-interleaved such that the sampled analog signal is fed to one of the plurality of sub-ADCs at a time sequentially,

wherein at least one sub-ADC among the plurality of sub-ADCs is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits to be generated by each of the at least one sub-ADC while the sampled analog signal is sampled by each of the at least one sub-ADC.

11. The ADC of claim 10 , wherein each of the at least one sub-ADC includes a comparator configured to determine the MSB while the input signal is sampled.

12. The ADC of claim 10 , wherein the sub-ADCs are successive approximation register (SAR) ADCs.

13. The ADC of claim 10 , wherein the sub-ADCs are flash ADCs.

14. The ADC of claim 10 , wherein at least one of the sub-ADCs is a pipelined ADC.

15. A method for converting an analog signal to digital bits, comprising:

receiving an analog signal;

processing the analog signal with a plurality of sub-analog-to-digital converters (ADCs) that are pipelined, wherein each sub-ADC generates a pre-configured number of digital bits and a residue signal for a subsequent sub-ADC in a pipeline from an input signal to each sub-ADC, wherein a most-significant bit (MSB) of the pre-configured number of digital bits to be generated by each of at least one sub-ADC among the plurality of sub-ADCs is determined by each of the at least one sub-ADC while the input signal to each of the at least one sub-ADC is sampled by each of the at least one sub-ADC; and

combining digital bits output from the plurality of sub-ADCs to generate an ADC output.

16. The method of claim 15 , wherein each of the at least one sub-ADC includes a comparator configured to determine the MSB while the input signal is sampled.

17. The method of claim 15 , wherein the sub-ADCs are successive approximation register (SAR) ADCs.

18. The method of claim 15 , further comprising:

sampling the analog signal, wherein the sampled analog signal is fed to a first sub-ADC in the pipeline as the input signal to the first sub-ADC,

wherein the first sub-ADC includes a comparator configured to determine the MSB.

19. The method of claim 18 , further comprising:

buffering, with a buffer, the sampled analog signal; and

feeding the buffered sampled analog signal to the first sub-ADC in the pipeline as the input signal to the first sub-ADC.

20. The method of claim 15 , wherein the sub-ADCs are flash ADCs.