Information processing apparatus and memory access method

1. An information processing apparatus comprising:

a memory controller including

a command accepting block configured to accept an access request from a host processor to a memory, the access request being stored in a sorted manner in one of a plurality of request queues, each request queue having associated therewith a rule set;

a management command generating block configured to generate a management command for managing the memory, the management command being stored in a sorted manner in one of a plurality of command queues, each command queue having associated therewith a rule set; and

a command processing block configured to read from at least one of the plurality of request queues and the plurality of command queues;

wherein

the command processing block switches, with a timing in accordance with the rule sets associated with the plurality of request queues, the one request queue to another request queue or to another command queue for processing in a same phase or between phases; and

the command processing block switches, with a timing based on the rule sets associated with the plurality of command queues and a management command processing time limit, the command queue to another command queue or another request queue.

2. The information processing apparatus according to claim 1 , wherein

the plurality of request queues store the access request sorted by contents and priority of an access and sorted by contents of the access, and

the command processing block switches at a point at which a processing upper limit number or limit time set independently is reached.

3. The information processing apparatus according to claim 2 , wherein the command processing block switches with a timing in accordance with a rule set by the priority of this access.

4. The information processing apparatus according to claim 1 , wherein

at least one of the plurality of request queues and the plurality of command queues further include a given queue for storing a request for management processing issued by the management command generating block; and

the command processing block reads and further executes the request for management processing from the given queue.

5. The information processing apparatus according to claim 4 , wherein while the given queue in which to store the request for management processing is the read destination, the command processing block switches with a timing of passing of a time limit setting.

6. The information processing apparatus according to claim 4 , wherein while the given queue in which to store the request for management processing is the read destination, the command processing block switches with a timing of storing an access request having a predetermined priority into the another request queue or the another command queue.

7. The information processing apparatus according to claim 4 , wherein the command processing block sets the request for management processing with a timing of notification by the host processor.

8. The information processing apparatus according to claim 4 , wherein the command processing block separates, of the management processing, an interval in which a read processing request is read from an interval in which a write processing request is read.

9. The information processing apparatus according to claim 4 , wherein the management processing includes processing of saving data stored in a block to another block and then deleting the data of the original block.

10. The information processing apparatus according to claim 4 , wherein the management processing includes processing of copying data written to a single level cell region for recording one bit per memory cell to a triple level cell region for recording three bits per memory cell.

11. The information processing apparatus according to claim 4 , wherein the memory controller further includes a command adjusting block configured to change at least any one of rules set for the given queue and a limit of processing on a basis of at least one of a request amount of the management processing already stored in the given queue and forecast results of a timing with which the request of management processing is issued.

12. The information processing apparatus according to claim 4 , wherein the memory controller further includes a command adjusting block configured to request the host processor to control issue of an access request on the basis of at least one of a request amount of the management processing already stored in the given queue and forecast results of a timing with which the request of management processing is issued.

13. The information processing apparatus according to claim 1 , wherein from a queue collectively storing read requests having priorities higher than a predetermined standard, the command processing block sequentially reads and executes these read requests.

14. The information processing apparatus according to claim 1 , further comprising a NAND-type flash memory configured to store data to be requested for access from the host processor.

15. The information processing apparatus according to claim 1 , further comprising a host processor configured to execute information processing so as to issue, to the memory controller, the access request.

16. A method to be carried out by a memory controller, the method comprising:

accepting an access request from a host processor to a memory, the access request being stored in a sorted manner in one of a plurality of request queues, each request queue having associated therewith a rule set;

generating a management command for managing the memory, the management command being stored in a sorted manner in one of a plurality of command queues, each command queue having associated therewith a rule set; and

reading from at least one of the plurality of request queues and the plurality of command queues;

wherein

the reading switches, with a timing in accordance with the rule sets associated with the plurality of request queues, the one request queue to another request queue or to another command queue for processing in a same phase or between phases; and switches, with a timing based on the rule sets associated with the plurality of command queues and a management command processing time limit, the command queue to another command queue or another request queue.

17. A non-transitory, computer readable storage medium containing a computer program, configured to be executed by a computer, which causes the computer to carry out actions in conjunction with a memory controller, comprising:

accepting an access request from a host processor to a memory, the access request being stored in a sorted manner in one of a plurality of request queues, each request queue having associated therewith a rule set;

generating a management command for managing the memory, the management command being stored in a sorted manner in one of a plurality of command queues, each command queue having associated therewith a rule set; and reading from at least one of the plurality of request queues and the plurality of command queues;

wherein

the reading switches, with a timing in accordance with the rule sets associated with the plurality of request queues, the one request queue to another request queue or to another command queue for processing in a same phase or between phases; and switches, with a timing based on the rule sets associated with the plurality of command queues and a management command processing time limit, the command queue to another command queue or another request queue.