Pixel circuitry and drive method thereof, array substrate, and display panel
Embodiments of the present disclosure provide a pixel circuitry. The pixel circuitry includes a data write-in circuit, an initialization circuit, a sense circuit, a first capacitor, a second capacitor, a drive transistor, and a data signal supply circuit. The data write-in circuit supplies a data signal to a first node according to a first control signal. The initialization circuit supplies an initialization signal to a sense line according to a second control signal. The sense circuit couples a second node to the sense line according to the first control signal. The data signal supply circuit reads the voltage of the sense line according to a third control signal, determines a threshold voltage of the drive transistor according to the read voltage, and corrects an original data signal according to the threshold voltage to supply the corrected original data signal to the data line.
1. A pixel circuitry comprising:
a data write-in circuit configured to provide a data signal from a data line to a first node according to a first control signal from a first control signal terminal;
an initialization circuit configured to provide an initialization signal to a sense line according to a second control signal from a second control signal terminal;
a sense circuit configured to couple a second node to the sense line according to the first control signal, such that a voltage of the second node is equal to a voltage of the sense line;
a first capacitor configured to store a voltage difference between the first node and the second node;
a second capacitor configured to store the voltage of the sense line;
a drive transistor, wherein a control electrode of the drive transistor is coupled to the first node, wherein a first electrode of the drive transistor is coupled to a first voltage signal terminal, wherein a second electrode of the drive transistor is coupled to the second node, and wherein the drive transistor is configured to provide a drive current to a light emitting device; and
a data signal supply circuit configured to: read the voltage of the sense line according to a third control signal from a third control signal terminal, determine a threshold voltage of the drive transistor according to the read voltage, and correct an original data signal from a data signal terminal according to the threshold voltage to supply the corrected original data signal to the data line.
2. The pixel circuitry according to claim 1 , wherein the data signal supply circuit comprises:
a read circuit configured to read the voltage of the sense line according to the third control signal;
a determination circuit configured to determine the threshold voltage of the drive transistor according to the read voltage; and
a supply circuit configured to correct the original data signal according to the threshold voltage to supply the corrected original data signal to the data line.
3. The pixel circuitry according to claim 2 , wherein the data signal supply circuit further comprises:
an analog-to-digital conversion circuit configured to convert the threshold voltage to a digital signal; and
a storage circuit configured to store the threshold voltage in the form of the digital signal.
4. The pixel circuitry according to claim 2 , further comprising:
a first reference circuit configured to supply a first reference signal to the data line according to a fourth control signal from a fourth control signal terminal.
5. The pixel circuitry according to claim 2 , further comprising:
a second reference circuit configured to supply a second reference signal to the sense line according to a fifth control signal from a fifth control signal terminal.
6. The pixel circuitry according to claim 1 , wherein the data write-in circuit comprises:
a first transistor, wherein a control electrode of the first transistor is coupled to the first control signal terminal, wherein a first electrode of the first transistor is coupled to the data line, and wherein a second electrode of the first transistor is coupled to the first node.
7. The pixel circuitry according to claim 1 , wherein the initialization circuit comprises:
a second transistor, wherein a control electrode of the second transistor is coupled to the second control signal terminal, wherein a first electrode of the second transistor is coupled to the initialization signal, and wherein a second electrode of the second transistor is coupled to the sense line.
8. The pixel circuitry according to claim 1 , wherein the sense circuit comprises:
a third transistor, wherein a control electrode of the third transistor is coupled to the first control signal, wherein a first electrode of the third transistor is coupled to the sense line, and wherein a second electrode of the third transistor is coupled to the second node.
9. The pixel circuitry according to claim 1 , further comprising:
a first reference circuit configured to supply a first reference signal to data line according to a fourth control signal from a fourth control signal terminal.
10. The pixel circuitry according to claim 9 , wherein the first reference circuit comprises:
a fourth transistor, wherein a control electrode of the fourth transistor is coupled to the fourth control signal terminal, wherein a first electrode of the fourth transistor is coupled to the first reference signal terminal, and wherein a second electrode of the fourth transistor is coupled to the data line.
11. The pixel circuitry according to claim 1 , further comprising:
a second reference circuit configured to supply a second reference signal to the sense line according to a fifth control signal from a fifth control signal terminal.
12. The pixel circuitry according to claim 11 , wherein the second reference circuit comprises:
a fifth transistor, wherein a control electrode of the fifth transistor is coupled to the fifth control signal terminal, wherein a first electrode of the fifth transistor is coupled to the second reference signal, and wherein a second electrode of the fifth transistor is coupled to the sense line.
13. A method for driving the pixel circuitry according to claim 1 , the method comprising:
in a non-display phase:
under control of a first control signal and a second control signal, supplying a data signal from a data line to a first node, supplying an initialization signal to a sense line, and ensuring a voltage of the sense line to be equal to a voltage of the second node;
under control of the first control signal, keeping supplying the data signal to the first node, and under control of a voltage of the first node, charging a first capacitor and a second capacitor by a drive current driving a drive transistor;
under control of a third control signal, reading the voltage of the sense line, and determining a threshold voltage of the drive transistor according to the read voltage; and
in a display phase, correcting an original data signal from the data signal terminal according to the threshold voltage to supply the corrected original data signal to the data line, and supplying the data signal from the data line to the first node under control of a first control signal to drive the drive transistor to supply the drive current.
14. The method according to claim 13 , wherein the pixel circuitry comprises a first reference circuit, wherein the first reference circuit is configured to supply a first reference signal to the data line according to a fourth control signal from a fourth control signal terminal, the method further comprising:
in the non-display phase, supplying a first reference signal to the data line under control of the fourth control signal.
15. The method according to claim 13 , wherein the pixel circuitry comprises a second reference circuit, wherein the second reference circuit is configured to supply a second reference signal to the sense line according to a fifth control signal from a fifth control signal terminal, the method further comprising:
in the display phase, supplying the second reference signal to the sense line under control of the fifth control signal.
16. The method according to claim 13 , wherein a scan frequency of the non-display phase is lower than a scan frequency of the display phase.
17. An array substrate, comprising a plurality of pixel circuitries according to claim 1 ,
wherein a drive transistor, a data write-in circuit, a sense circuit, and a first capacitor of each of the pixel circuitries are arranged in an active display area of the array substrate; and
a second capacitor, an initialization circuit, and a data signal supply circuit of each of the pixel circuitries are arranged in a peripheral area of the array substrate.
18. A display panel comprising an array substrate according to claim 17 .
19. The array substrate according to claim 17 , wherein the data signal supply circuit comprises:
a read circuit configured to read the voltage of the sense line according to the third control signal;
a determination circuit configured to determine the threshold voltage of the drive transistor according to the read voltage; and
a supply circuit configured to correct the original data signal according to the threshold voltage to supply the corrected original data signal to the data line.
20. The array substrate according to claim 19 , wherein the data signal supply circuit further comprises:
an analog-to-digital conversion circuit configured to convert the threshold voltage to a digital signal; and
a storage circuit configured to store the threshold voltage in the form of the digital signal.