Semiconductor storage device having a memory unit bonded to a circuit unit and connected to each other by a plurality of bonding metals
A semiconductor storage device includes a memory unit and a circuit unit bonded to the memory unit. The memory unit includes first and second memory cells, first and second bit lines respectively connected to the first and second memory cells, and first and second bonding metals respectively connected to the first and second bit lines. The circuit unit includes a sense amplifier unit including a first wire, a third bonding metal connected with the first wire and opposed to the first bonding metal, and a fourth bonding metal connected with the first wire and opposed to the second bonding metal.
1. A semiconductor storage device comprising:
a memory unit that includes first and second memory cells, first and second bit lines respectively connected to the first and second memory cells, and first and second bonding metals respectively connected to the first and second bit lines; and
a circuit unit bonded to the memory unit, the circuit unit including a sense amplifier module including a first wire, a third bonding metal connected to the first wire and opposed to the first bonding metal, and a fourth bonding metal connected to the first wire and opposed to the second bonding metal, wherein
the first and second bit lines each extend in a first direction, are aligned along the first direction, and are separated in the first direction.
2. The semiconductor storage device according to claim 1 , wherein
the sense amplifier module includes a first sense amplifier connected between the third bonding metal and the first wire, a second sense amplifier connected between the fourth bonding metal and the first wire, and a latch circuit that is connected to the first wire and shared by the first sense amplifier and the second sense amplifier.
3. The semiconductor storage device according to claim 1 , wherein
the memory unit further includes a third memory cell, a third bit line connected to the third memory cell, and a fifth bonding metal connected to the third bit line, and
the circuit unit further includes a sixth bonding metal that is connected to the first wire and faces the fifth bonding metal.
4. A semiconductor storage device comprising:
a memory unit that includes first and second memory cells, first and second bit lines respectively connected to the first and second memory cells, and first and second bonding metals respectively connected to the first and second bit lines; and
a circuit unit bonded to the memory unit, the circuit unit including a sense amplifier unit including a first wire, a third bonding metal connected to the first wire and opposed to the first bonding metal, and a fourth bonding metal connected to the first wire and opposed to the second bonding metal, wherein
the circuit unit further includes a first local amplifier unit connected to the first bit line, a second local amplifier unit connected to the second bit line, and a global bit line connected to the first local amplifier unit and the second local amplifier unit, and
the sense amplifier unit is connected between the first wire and the global bit line.
5. The semiconductor storage device according to claim 4 , wherein
the first local amplifier unit includes a first transistor connected between the first bit line and the global bit line, and a second transistor that is connected between the global bit line and a ground line and whose gate is connected to a first node between the first bit line and the first transistor, and
the second local amplifier unit includes a third transistor connected between the second bit line and the global bit line, and a fourth transistor that is connected between the global bit line and a ground line and whose gate is connected to a second node between the second bit line and the third transistor.
6. The semiconductor storage device according to claim 5 , wherein
the circuit unit further includes a controller that executes a read operation,
the first local amplifier unit further includes a fifth transistor connected to the first node,
the second local amplifier unit further includes a sixth transistor connected to the second node,
the controller applies a ground voltage to the second bit line via the sixth transistor in a read operation in which the first memory cell is selected, and
the controller applies the ground voltage to the first bit line via the fifth transistor in a read operation in which the second memory cell is selected.
7. The semiconductor storage device according to claim 4 , wherein
the first local amplifier unit includes a seventh transistor connected between the first bit line and the global bit line, an eighth transistor connected between the first bit line and a power supply line, a ninth transistor connected between the first bit line and a first sense node, a tenth transistor whose gate is connected to the first sense node, and an eleventh transistor connected between the tenth transistor and the global bit line, and
the second local amplifier unit includes a twelfth transistor connected between the second bit line and the global bit line, a thirteenth transistor connected between the second bit line and the power supply line, a fourteenth transistor connected between the first bit line and a second sense node, a fifteenth transistor whose gate is connected to the second sense node, and a sixteenth transistor connected between the fifteenth transistor and the global bit line.
8. The semiconductor storage device according to claim 7 , wherein
the circuit unit further includes a controller that executes a write operation, and
the controller
controls the seventh transistor to an ON state and the twelfth transistor to an OFF state in a write operation in which the first memory cell is selected, and
controls the seventh transistor to an OFF state and the twelfth transistor to an ON state in a write operation in which the second memory cell is selected.
9. The semiconductor storage device according to claim 1 , wherein
the memory unit includes a plurality of first conductor layers that are separated from each other, first pillars that pass through the plurality of first conductor layers, a plurality of second conductor layers that are separated from each other, second pillars that pass through the plurality of second conductor layers, and third conductor layers and fourth conductor layers that are respectively connected to the first pillars and second pillars,
the first memory cell is located at an intersection portion between one of the first pillars and one of the first conductor layers,
the second memory cell is located at an intersection portion between one of the second pillars and one of the second conductor layers,
the first bit line is one of the third conductor layers and the second bit line is one of the fourth conductor layers, and
each of the first bonding metal, the second bonding metal, the third bonding metal, and the fourth bonding metal contains copper.
10. A semiconductor storage device comprising:
a memory unit including
a first memory cell,
a first word line extending in a first direction and connected to a gate of the first memory cell,
a first bit line extending in a second direction different from the first direction and connected to the first memory cell,
a second memory cell,
a second word line extending in the first direction and connected to a gate of the second memory cell,
a second bit line extending in the second direction and connected to the second memory cell,
a first bonding metal provided at one side of the first bit line in a third direction different from the first direction and the second direction and connected to the first bit line, and
a second bonding metal provided at the one side of the second bit line in the third direction and connected to the second bit line; and
a circuit unit including
a first sense amplifier,
a second sense amplifier,
a first latch circuit,
a first wire connected to the first sense amplifier, the second sense amplifier, and the first latch circuit,
a third bonding metal provided at the other side of the first sense amplifier in the third direction, connected to the first sense amplifier, and opposed to the first bonding metal for bonding thereto, and
a fourth bonding metal provided at the other side of the second sense amplifier in the third direction, connected to the second sense amplifier, and opposed to the second bonding metal for bonding thereto, wherein
the first and second bit lines are aligned along the second direction and are separated in the second direction.
11. The semiconductor storage device according to claim 10 , wherein
the first latch circuit is shared by the first sense amplifier and the second sense amplifier.
12. The semiconductor storage device according to claim 10 , wherein
the memory unit further includes
a third memory cell,
a third word line extending in the first direction and connected to a gate of the third memory cell,
a third bit line extending in the second direction and connected to the third memory cell,
a fifth bonding metal provided at one side of the third bit line in the third direction and connected to the third bit line, and
the circuit unit further includes
a third sense amplifier, and
a sixth bonding metal provided at the other side of the third sense amplifier in the third direction, connected to the third sense amplifier, and opposed to the fifth bonding metal for bonding thereto.
13. A semiconductor storage device comprising:
a memory unit including
a first memory cell,
a first word line extending in a first direction and connected to a gate of the first memory cell,
a first bit line extending in a second direction different from the first direction and connected to the first memory cell,
a second memory cell,
a second word line extending in the first direction and connected to a gate of the second memory cell,
a second bit line extending in the second direction and connected to the second memory cell,
a first bonding metal provided at one side of the first bit line in a third direction different from the first direction and the second direction and connected to the first bit line, and
a second bonding metal provided at the one side of the second bit line in the third direction and connected to the second bit line; and
a circuit unit including
a first sense amplifier,
a second sense amplifier,
a first latch circuit,
a first wire connected to the first sense amplifier, the second sense amplifier, and the first latch circuit,
a third bonding metal provided at the other side of the first sense amplifier in the third direction, connected to the first sense amplifier, and opposed to the first bonding metal for bonding thereto, and
a fourth bonding metal provided at the other side of the second sense amplifier in the third direction, connected to the second sense amplifier, and opposed to the second bonding metal for bonding thereto, wherein
the circuit unit further includes a first local amplifier unit connected to the first bit line, a second local amplifier unit connected to the second bit line, and a global bit line connected to the first local amplifier unit and the second local amplifier unit, and
the sense amplifier unit is connected between the first wire and the global bit line.
14. The semiconductor storage device according to claim 13 , wherein
the first local amplifier unit includes a first transistor connected between the first bit line and the global bit line, and a second transistor that is connected between the global bit line and a ground line and whose gate is connected to a first node between the first bit line and the first transistor, and
the second local amplifier unit includes a third transistor connected between the second bit line and the global bit line, and a fourth transistor that is connected between the global bit line and a ground line and whose gate is connected to a second node between the second bit line and the third transistor.
15. The semiconductor storage device according to claim 14 , wherein
the circuit unit further includes a controller that executes a read operation,
the first local amplifier unit further includes a fifth transistor connected to the first node,
the second local amplifier unit further includes a sixth transistor connected to the second node,
the controller applies a ground voltage to the second bit line via the sixth transistor in a read operation in which the first memory cell is selected, and
the controller applies the ground voltage to the first bit line via the fifth transistor in a read operation in which the second memory cell is selected.
16. The semiconductor storage device according to claim 13 , wherein
the first local amplifier unit includes a seventh transistor connected between the first bit line and the global bit line, an eighth transistor connected between the first bit line and a power supply line, a ninth transistor connected between the first bit line and a first sense node, a tenth transistor whose gate is connected to the first sense node, and an eleventh transistor connected between the tenth transistor and the global bit line, and
the second local amplifier unit includes a twelfth transistor connected between the second bit line and the global bit line, a thirteenth transistor connected between the second bit line and the power supply line, a fourteenth transistor connected between the first bit line and a second sense node, a fifteenth transistor whose gate is connected to the second sense node, and a sixteenth transistor connected between the fifteenth transistor and the global bit line.
17. The semiconductor storage device according to claim 16 , wherein
the circuit unit further includes a controller that executes a write operation, and
the controller
controls the seventh transistor to an ON state and the twelfth transistor to an OFF state in a write operation in which the first memory cell is selected, and
controls the seventh transistor to an OFF state and the twelfth transistor to an ON state in a write operation in which the second memory cell is selected.
18. The semiconductor storage device according to claim 10 , wherein
the memory unit includes a plurality of first conductor layers that are separated from each other, first pillars that pass through the plurality of first conductor layers, a plurality of second conductor layers that are separated from each other, second pillars that pass through the plurality of second conductor layers, and third conductor layers and fourth conductor layers that are respectively connected to the first pillars and second pillars,
the first memory cell is located at an intersection portion between one of the first pillars and one of the first conductor layers,
the second memory cell is located at an intersection portion between one of the second pillars and one of the second conductor layers,
the first bit line is one of the third conductor layers and the second bit line is one of the fourth conductor layers, and
each of the first bonding metal, the second bonding metal, the third bonding metal, and the fourth bonding metal contains copper.