Non-volatile memory device utilizing dummy memory block as pool capacitor

1. A non-volatile memory device, comprising:

a plurality of memory blocks and at least one dummy block adjacent to the plurality of memory blocks, wherein each of the plurality of memory blocks comprises an alternating layer stack on a substrate, a plurality of channel holes in the alternating layer stack, and strings of memory cells disposed along the plurality of channel holes, wherein the at least one dummy block comprises an alternating dummy layer stack on the substrate, and wherein the alternating dummy layer stack comprises multiple conductive layers and multiple dielectric layers alternately laminated on one another; and

a peripheral circuit region for supporting operations of the plurality of memory blocks.

2. The non-volatile memory device according to claim 1 , no through hole is disposed in the alternating dummy layer stack to penetrate through the multiple conductive layers and multiple dielectric layers.

3. The non-volatile memory device according to claim 1 , wherein the at least one dummy block further comprises:

a conductor region in the substrate, wherein the conductor region is disposed directly under the multiple conductive layers so as to form a capacitor between the conductor region and one of the multiple conductive layers adjacent to the conductor region.

4. The non-volatile memory device according to claim 3 , wherein the conductor region is configured to be electrically connected to a ground potential.

5. The non-volatile memory device according to claim 3 , wherein the conductor region is a heavily doped diffusion region.

6. The non-volatile memory device according to claim 3 , wherein the conductor region is a silicided metal region.

7. The non-volatile memory device according to claim 1 , wherein the at least one dummy block further comprises:

stair structures at two opposite ends of the dummy block; and

contacts disposed on the stair structures and electrically connected to the multiple conductive layers.

8. The non-volatile memory device according to claim 7 , wherein the multiple conductive layers are configured to be sequentially and alternately biased to a power source and a ground potential via the contacts disposed on the stair structures, thereby forming capacitors between the multiple conductive layers, wherein the multiple dielectric layers act as a capacitor dielectric.

9. The non-volatile memory device according to claim 8 , wherein the power source comprises an internal power source or an external power source.

10. The non-volatile memory device according to claim 7 , wherein at least two neighboring conductive layers of the multiple conductive layers are configured to be biased to a same power source via the contacts disposed on the stair structures.

11. The non-volatile memory device according to claim 1 , wherein the at least one dummy block is disposed at an outskirt of one of the plurality of memory blocks.

12. The non-volatile memory device according to claim 1 , wherein the at least one dummy block is split into multiple sub-blocks.

13. The non-volatile memory device according to claim 1 , wherein the peripheral circuit region comprises a plurality of pool capacitors.

14. A non-volatile memory device, comprising:

a plurality of memory blocks and at least one dummy block configured to form a pool capacitor for suppressing power noise, wherein the at least one dummy block comprises a substrate, a conductor region in the substrate, and an alternating dummy layer stack on the conductor region, and wherein the alternating dummy layer stack comprises multiple conductive layers and multiple dielectric layers alternately laminated on one another.

15. The non-volatile memory device according to claim 14 , no through hole is disposed in the alternating dummy layer stack to penetrate through the multiple conductive layers and multiple dielectric layers.

16. The non-volatile memory device according to claim 14 , wherein a capacitor is formed between the conductor region and one of the multiple conductive layers adjacent to the conductor region.

17. The non-volatile memory device according to claim 14 , wherein the conductor region is electrically connected to a ground potential.

18. The non-volatile memory device according to claim 14 , wherein the conductor region is a heavily doped diffusion region.

19. The non-volatile memory device according to claim 14 , wherein the conductor region is a silicided metal region.

20. The non-volatile memory device according to claim 14 , wherein the dummy block is disposed at an outskirt of the plurality of memory blocks.

21. The non-volatile memory device according to claim 14 , wherein the dummy block is split into multiple sub-blocks.