Semiconductor device
In a first cell region of a semiconductor substrate, a first semiconductor element is formed. In a second cell region of semiconductor substrate, a second semiconductor element is formed. First semiconductor element includes a first electrode and a first p region. Second semiconductor element includes a second electrode and a second p region. First electrode and second electrode are separated from each other. First p region and second p region are separated from each other.
1. A semiconductor device comprising:
a semiconductor substrate having a front face, a back face, and an n− region between the front face and the back face;
a front electrode disposed on the front face; and
a back electrode disposed on the back face,
the semiconductor substrate including a first cell region, and a second cell region adjacent to the first cell region,
the first cell region being formed with a first semiconductor element,
the second cell region being formed with a second semiconductor element,
the front electrode including a first electrode formed in the first cell region, and a second electrode formed in the second cell region,
the first semiconductor element including the first electrode, and a first p region formed on a side of the front face of the first cell region,
the second semiconductor element including the second electrode, and a second p region formed on a side of the front face of the second cell region,
the n− region being positioned between the first p region and the second p region,
the first electrode and the second electrode being separated from each other,
the first p region and the second p region being separated from each other, and being located inside the n− region.
2. The semiconductor device according to claim 1 , wherein the first semiconductor element is a first transistor having trench gate structure, and the second semiconductor element is a second transistor having trench gate structure.
3. The semiconductor device according to claim 1 , wherein the first semiconductor element is a first transistor having planar gate structure, and the second semiconductor element is a second transistor having planar gate structure.
4. The semiconductor device according to claim 2 , further comprising:
a gate wiring electrically connected with a first gate electrode of the first semiconductor element, and a second gate electrode of the second semiconductor element,
in plan view of the front face of the semiconductor substrate, the gate wiring being disposed on a boundary between the first cell region and the second cell region.
5. The semiconductor device according to claim 1 , wherein the first semiconductor element is a first diode, and the second semiconductor element is a second diode.
6. The semiconductor device according to claim 1 , wherein
the semiconductor substrate further includes an n+ region disposed between the first p region of the first semiconductor element and the second p region of the second semiconductor element in plan view of the front face of the semiconductor substrate, and
the n+ region is separated from the first p region and the second p region.