Structure for metal gate electrode and method of fabrication
A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.
1. A semiconductor device, comprising:
a channel component of a transistor; and
a gate component disposed over the channel component, wherein the gate component includes:
a dielectric layer;
a first work function metal layer disposed over the dielectric layer;
a fill-metal layer disposed over the first work function metal layer; and
a second work function metal layer disposed over the fill-metal layer
wherein a topmost surface of the fill-metal layer is more vertically elevated than a topmost surface of the first work function metal layer or a topmost surface of the second work function metal layer.
2. The semiconductor device of claim 1 , wherein at least a portion of the fill-metal layer has a concave profile in a cross-sectional view.
3. The semiconductor device of claim 2 , wherein:
an upper portion of the fill-metal layer has a U-shape cross-sectional profile; and
a lower portion of the fill-metal layer has an “I”-shape cross-sectional profile.
4. The semiconductor device of claim 2 , wherein the concave profile in the cross-sectional view is defined at least in part by a plurality of vertically-protruding side portions of the fill-metal layer, wherein the semiconductor device further comprises a gate contact that is disposed over the fill-metal layer, and wherein a portion of the gate contact is disposed between the vertically-protruding side portions of the fill-metal layer.
5. The semiconductor device of claim 4 , wherein the gate contact is in physical contact with the first work function metal layer and with the second work function metal layer.
6. The semiconductor device of claim 4 , wherein the fill-metal layer protrudes vertically into the gate contact.
7. The semiconductor device of claim 1 , wherein:
the first work function metal layer includes a first type work function metal;
the second work function metal layer includes a second type work function metal; and
the first type work function metal is a p-type work function metal, and the second type work function metal is an n-type work function metal, or vice versa.
8. The semiconductor device of claim 7 , wherein:
the gate component further includes a third work function metal layer that is disposed over the fill-metal layer but below the second work function metal layer; and
the third work function metal layer includes the first type work function metal.
9. The semiconductor device of claim 8 , wherein:
the gate component further includes a fourth work function metal layer that is disposed over the second work function metal layer; and
the fourth work function metal layer includes the first type work function metal.
10. The semiconductor device of claim 1 , wherein the dielectric layer includes an interfacial layer and a high-k dielectric layer disposed over the interfacial layer.
11. A gate structure of a transistor, comprising:
a gate dielectric layer;
a first work function metal layer located over the gate dielectric layer;
a fill-metal layer located over the first work function metal layer, wherein the fill-metal layer includes a U-shaped recess; and
a second work function metal layer located in the U-shaped recess;
wherein a topmost surface of the fill-metal layer is more elevated vertically than topmost surfaces of the first work function metal layer and the second work function metal layer.
12. The gate structure of claim 11 , wherein:
an upper portion of the fill-metal layer defines the U-shaped recess; and
a lower portion of the fill-metal layer is located below the U-shaped recess and has a vertical bar shape.
13. The gate structure of claim 11 , further comprising:
a third work function metal layer that is located over the fill-metal layer but below the second work function metal layer; and
a fourth work function metal layer that is located over the second work function metal layer.
14. The gate structure of claim 13 , wherein:
the first, third, and fourth work function metal layers each contain a first type work function metal; and
the second work function metal layer contains a second type work function metal different from the first type work function metal.
15. A semiconductor device, comprising:
a channel of a transistor; and
a gate structure disposed over the channel, wherein the gate structure includes:
an interfacial layer;
a high-k dielectric layer disposed over the interfacial layer;
a first work function metal layer disposed over the high-k dielectric layer;
a fill-metal layer disposed over the first work function metal layer;
a second work function metal layer disposed over the fill-metal layer;
a third work function metal layer disposed over the second work function metal layer; and
a fourth work function metal layer disposed over the third work function metal layer, wherein the first work function metal layer, the second work function metal layer, and the fourth work function metal layer have a same type of work function metal, and wherein the third work function metal layer has a different type of work function metal than the first work function metal layer, the second work function metal layer, and the fourth work function metal layer.
16. The semiconductor device of claim 15 , wherein the fill-metal layer includes a recessed surface in a cross-sectional view.
17. The semiconductor device of claim 16 , wherein the recessed surface resembles a letter “U”.
18. The semiconductor device of claim 15 , wherein the fill-metal layer includes a plurality of vertically-protruding side portions.
19. The semiconductor device of claim 15 , further comprising: a gate contact, wherein the gate contact is in physical contact with at least the first work function metal layer.
20. The semiconductor device of claim 15 , wherein an uppermost surface of the fill-metal layer is disposed over an uppermost surface of the first work function metal layer and over an uppermost surface of the third work function metal layer.