IP Library Granted Patent US 11,288,096
Granted Patent B2
US 11,288,096 · App. 16/653,185 · Granted Mar 29, 2022

System and method of balancing mixed workload performance

Inventors: Rahul Ugale (Santa Clara, CA); Colin Zou (San Jose, CA)
Assignee: EMC IP HOLDING COMPANY LLC
G06F9/4881G06F9/505G06F9/5038G06F11/1446G06F11/3024G06F12/0253G06F2212/401
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Quick Facts
Patent No.
US 11,288,096
App. No.
16/653,185
Filed
Oct 15, 2019
Granted
Mar 29, 2022
Kind
B2
Art Unit
2196
USPC
718/102
Abstract

One embodiment provides a computer implemented method of balancing mixed workload performance including monitoring the compression and decompression workload at a hardware accelerator using the hardware accelerator quality of service (QoS) scheduler; monitoring the compression and decompression workload at a CPU using the CPU QoS scheduler; comparing the workload at the hardware accelerator and the workload at the CPU; and allocating tasks between the hardware accelerator and the CPU to obtain an optimal bandwidth at the hardware accelerator and the CPU.

Claims (49)

1. A computer implemented method of balancing mixed workload performance, the method comprising:

monitoring compression and decompression workload at a hardware accelerator using a hardware accelerator quality of service (QoS) scheduler;

monitoring compression and decompression workload at a central processing unit (CPU) using a CPU QoS scheduler, wherein the compression and decompression workload includes one or more of backup jobs, restore jobs, garbage collection jobs, and replication jobs;

comparing the workload at the hardware accelerator and the workload at the CPU; and

allocating tasks between the hardware accelerator and the CPU to obtain an optimal bandwidth at the hardware accelerator and the CPU.

2. The computer implemented method as in claim 1 , wherein the hardware accelerator is a QuickAssist Technology gzip accelerator.

3. The computer implemented method as in claim 1 , further comprising:

receiving workload priorities from a user prioritizing the backup jobs, restore jobs, garbage collection jobs, and replication jobs.

4. The computer implemented method as in claim 1 , wherein the optimal bandwidth includes a balanced bandwidth between the hardware accelerator and the CPU.

5. The computer implemented method as in claim 1 , further comprising:

aggregating multiple source data buffers into a compression unit;

submitting a scatter gather list and a destination buffer to the hardware accelerator;

calculating a first checksum of result data from the destination buffer;

adding a zlib header to the result data; and

adding the first checksum as a zlib footer to the result data.

6. A data compression system comprising:

a hardware accelerator for compressing and decompressing data;

a hardware accelerator quality of service (QoS) scheduler configured to monitor workload of and assign compression and decompression jobs to the hardware accelerator;

a central processing unit (CPU) QoS scheduler configured to monitor workload of a CPU and assign compression and decompression jobs to the CPU; and

mixed workload performance logic configured to:

monitor compression and decompression workload at the hardware accelerator using the hardware accelerator QoS scheduler;

monitor compression and decompression workload at the CPU using the CPU QoS scheduler;

compare the workload at the hardware accelerator and the workload at the CPU, wherein the compression and decompression workload at the hardware accelerator and at the CPU includes one or more of backup jobs, restore jobs, garbage collection jobs, and replication jobs; and

allocate tasks between the hardware accelerator and the CPU to obtain an optimal bandwidth at the hardware accelerator and the CPU.

7. The data compression system as in claim 6 , wherein the hardware accelerator is a QuickAssist Technology gzip accelerator.

8. The data compression system as in claim 6 , wherein the mixed workload performance logic is further configured to:

receive workload priorities from a user prioritizing the backup jobs, restore jobs, garbage collection jobs, and replication jobs.

9. The data compression system as in claim 6 , wherein the optimal bandwidth includes a balanced bandwidth between the hardware accelerator and the CPU.

10. The data compression system as in claim 6 , further comprising compression logic configured to:

aggregate multiple source data buffers into a compression unit;

submit a scatter gather list and a destination buffer to the hardware accelerator;

calculate a first checksum of result data from the destination buffer;

add a zlib header to the result data; and

add the first checksum as a zlib footer to the result data.

11. A non-transitory computer-readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform a mixed workload performance operation, the operation comprising:

monitoring compression and decompression workload at a hardware accelerator using a hardware accelerator QoS scheduler;

monitoring compression and decompression workload at a central processing unit (CPU) using a CPU QoS scheduler;

comparing the workload at the hardware accelerator and the workload at the CPU, wherein the compression and decompression workload at the hardware accelerator and at the CPU includes one or more of backup jobs, restore jobs, garbage collection jobs, and replication jobs; and

allocating tasks between the hardware accelerator and the CPU to obtain an optimal bandwidth at the hardware accelerator and the CPU.

12. The non-transitory computer-readable medium as in claim 11 , wherein the hardware accelerator is a QuickAssist Technology gzip accelerator.

13. The non-transitory computer-readable medium as in claim 11 , wherein the mixed workload performance operation is further configured to:

receive workload priorities from a user prioritizing the backup jobs, restore jobs, garbage collection jobs, and replication jobs.

14. The non-transitory computer-readable medium as in claim 11 , wherein the optimal bandwidth includes a balanced bandwidth between the hardware accelerator and the CPU.

15. The non-transitory computer-readable medium as in claim 11 , wherein the one or more processors are further configured to perform a compression operation to:

aggregate multiple source data buffers into a compression unit;

submit a scatter gather list and a destination buffer to the hardware accelerator;

calculate a first checksum of result data from the destination buffer;

add a zlib header to the result data; and

add the first checksum as a zlib footer to the result data.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (051302/0528) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.); SECUREWORKS CORP.
Reel/Frame 060438/0593 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST AT REEL 051449 FRAME 0728 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.; SECUREWORKS CORP.; EMC CORPORATION
Reel/Frame 058002/0010 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Dec 31, 2019
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.; SECUREWORKS CORP.; EMC CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 051449/0728 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Dec 16, 2019
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.; SECUREWORKS CORP.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 051302/0528 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2019
From: UGALE, RAHUL; ZOU, COLIN
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 050721/0008 →
Continuity (1)
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