Gate-driving unit circuit having pre-pull down sub-circuit, gate driver on array circuit, driving method, and display apparatus thereof

1. A gate-driving unit circuit comprising:

an input sub-circuit coupled to an input terminal and a pull-up node, and configured to charge a pull-up node to a turn-on voltage level;

a pre-pull-down sub-circuit coupled to a pull-down node, a pre-pull-down node, and a reference voltage terminal, and configured to pull down voltage levels at the pull-down node and the pre-pull-down node to a turn-off voltage level before the pull-up node is charged to the turn-on voltage level;

a pull-down sub-circuit coupled to the input sub-circuit via the pull-up node, coupled to the pre-pull-down sub-circuit via the pre-pull-down node, coupled to the pull-down node and the reference voltage terminal, and configured to pull down a voltage level at the pull-down node to a turn-off voltage level;

a pull-down control sub-circuit coupled to the pre-pull-down sub-circuit via the pre-pull-down node and the pull-down sub-circuit via the pre-pull-down node or the pull-down node, and configured to pull down a voltage level at the pre-pull-down node and the pull-down node to the turn-off voltage level;

a noise-reduction sub-circuit coupled to the pull-down control sub-circuit and the pull-down sub-circuit via the pull-down node, coupled to the pull-up node, an output terminal, and the reference voltage terminal, and configured to stabilize voltage levels of the pull-up node and the output terminal; and

an output sub-circuit coupled to the pull-up node, a clock signal terminal, the output terminal, and configured to output a gate-driving signal to the output terminal.

2. The gate-driving unit circuit of claim 1 , wherein the input sub-circuit comprises a first transistor having a gate electrode and a first electrode coupled to the input terminal and a second electrode coupled to the pull-up node.

3. The gate-driving unit circuit of claim 1 , wherein the pull-down control sub-circuit comprises a fifth transistor and a sixth transistor, the fifth transistor having a gate electrode and a first electrode coupled to a power-supply voltage terminal, and a second electrode coupled to the pre-pull-down node; the sixth transistor having a gate electrode coupled to the pre-pull-down node, a first electrode coupled to the first electrode of the fifth transistor, and a second electrode coupled to the pull-down node.

4. The gate-driving unit circuit of claim 1 , wherein the pre-pull-down sub-circuit comprises an eleventh transistor and a twelfth transistor, the eleventh transistor having a gate electrode coupled to a pre-pull-down signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pre-pull-down node; the twelfth transistor having a gate electrode coupled to the pre-pull-down signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-down node.

5. The gate-driving unit circuit of claim 1 , wherein the pull-down sub-circuit comprises a seventh transistor and an eighth transistor, the seventh transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pre-pull-down node, the eighth transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-down node.

6. The gate-driving unit circuit of claim 1 , further comprising a reset sub-circuit coupled to the pull-up node, the output terminal, a reset signal terminal, and the reference voltage terminal, and configured to reset voltage levels of the pull-up node and the output terminal; wherein the reset sub-circuit comprises a second transistor and a fourth transistor, the second transistor having a gate electrode coupled to a reset signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-up node, the fourth transistor having a gate electrode coupled to the reset signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the output terminal.

7. The gate-driving unit circuit of claim 1 , wherein the noise-reduction sub-circuit comprises a ninth transistor and a tenth transistor, the ninth transistor having a gate electrode coupled to the pull-down node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-up node, the tenth transistor having a gate electrode coupled to the pull-down node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the output terminal.

8. The gate-driving unit circuit of claim 1 , wherein the output sub-circuit comprises a third transistor and a storage capacitor, the third transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to a clock signal terminal, and a second electrode coupled to the output terminal, and the storage capacitor having a first port coupled to the pull-up node and a second port coupled to the output terminal.

9. The gate-driving unit circuit of claim 1 , wherein the turn-on voltage level comprises a voltage level applicable to a gate electrode of a transistor that allows a first electrode of the transistor to be connected with a second electrode of the transistor, and the turn-off voltage level comprises a voltage level applicable to a gate electrode of a transistor that allows a first electrode of the transistor to be disconnected from a second electrode of the transistor.

10. A gate driver on array (GOA) circuit, comprising a plurality of gate-driving unit circuits cascaded in a multi-stage series, each of the plurality of gate-driving unit circuits being configured according to claim 1 , wherein the multi-stage series comprises at least a gate-driving unit circuit in an (N−2)-th stage coupled to a gate-driving unit circuit in an (N−1)-th stage which further is coupled to a gate-driving unit circuit in an N-th stage, wherein N is an integer greater than 2.

11. The GOA circuit of claim 10 , wherein the gate-driving unit circuit in each of the multi-stage series comprises:

a first transistor having a gate electrode and a first electrode commonly coupled to an input terminal and a second electrode coupled to a pull-up node;

a second transistor having a gate electrode coupled to a reset signal terminal, a first electrode coupled to a reference voltage terminal, and a second electrode coupled to the pull-up node;

a third transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to a clock signal terminal, and a second electrode coupled to an output terminal;

a fourth transistor having a gate electrode coupled to the reset signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the output terminal;

a fifth transistor having a gate electrode and a first electrode coupled to a power-supply voltage terminal, and a second electrode coupled to a pre-pull-down node;

a sixth transistor having a gate electrode coupled to the pre-pull-down node, a first electrode coupled to the first electrode of the fifth transistor, and a second electrode coupled to a pull-down node;

a seventh transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pre-pull-down node;

an eighth transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-down node;

a ninth transistor having a gate electrode coupled to the pull-down node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-up node;

a tenth transistor having a gate electrode coupled to the pull-down node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the output terminal;

an eleventh transistor having a gate electrode coupled to the pre-pull-down signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pre-pull-down node;

a twelfth transistor having a gate electrode coupled to the pre-pull-down signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-down node; and

a storage capacitor having a first port coupled to the pull-up node and a second port coupled to the output terminal.

12. The GOA circuit of claim 11 , wherein the gate-driving unit circuit in the (N−2)-th stage comprises an output terminal connected to the input terminal of the gate-driving unit circuit in an N-th stage; the gate-driving unit circuit in the (N−1)-th stage comprises an input terminal connected to a pre-pull-down signal terminal of the gate-driving unit circuit in the N-th stage; and the gate-driving unit circuit in an (N+2)-th stage comprises an output terminal connected to the reset signal terminal of the gate-driving unit circuit in the N-th stage.

13. A method of driving a GOA circuit of claim 10 , comprising driving a gate-driving unit circuit in an N-th stage in an N-th cycle of displaying one frame of image progressively from one stage after another, wherein the N-th cycle comprises a duration commonly for every cycle including sequentially a first period, a second period, a third period, a fourth period, a fifth period, and a sixth period.

14. The method of claim 13 , wherein the driving a gate-driving unit circuit in the N-th stage comprises:

in the first period of the N-th cycle, keeping a pull-up node and an output terminal of the gate-driving unit circuit in an N-th stage to a turn-off voltage level under control of a voltage level at a pull-down node in the gate-driving unit circuit in an N-th stage;

in the second period of the N-th cycle, pulling down a voltage level at a pre-pull-down node and a voltage level at the pull-down node of the gate-driving unit circuit in the N-th stage to a turn-off voltage level under control of an input signal of the gate-driving unit circuit in the (N−1)-th stage before charging the pull-up node;

in the third period of the N-th cycle, keeping the voltage level of the pre-pull-down node and the voltage level of the pull-down node to the turn-off voltage level under control of the turn-on voltage level charged to the pull-up node;

in the fourth period of the N-th cycle, receiving an output signal from the gate-driving unit circuit in the (N−2)-th stage into an input terminal of the gate-driving unit circuit in the N-th stage, and storing the output signal at an pull-up node of the gate-driving unit circuit in the N-th stage for charging the pull-up node;

in the fifth period of the N-th cycle, outputting a gate-driving signal to a gate line of the N-th stage under control of a clock signal; and

in the sixth period of the N-th cycle, receiving an output signal from the gate-driving unit circuit in an (N+2)-th stage into a reset terminal of the gate-driving unit circuit in the N-th stage, and pulling down the voltage level at the pull-up node and the voltage level at the output terminal of the gate-driving unit circuit in the N-th stage.

15. The method of claim 14 , wherein pulling down the voltage level at the pre-pull-down node and the voltage level at the pull-down node of the gate-driving unit circuit in the N-th stage to the turn-off voltage level is performed at least during an (N−1)-th cycle or earlier before the N-th cycle.

16. The method of claim 15 , wherein pulling down the voltage level at the pre-pull-down node and the voltage level at the pull-down node comprises receiving an input signal of the turn-on voltage level by an input terminal of the gate-driving unit circuit in the (N−1)-th stage and passing the turn-on voltage level to a pre-pull-down signal terminal of the gate-driving unit circuit in the N-th stage to allow the pre-pull-down node and the pull-down node connected with a reference voltage terminal fixed at the turn-off voltage level.

17. The method of claim 14 , wherein keeping a pull-up node and an output terminal of the gate-driving unit circuit in an N-th stage to a turn-off voltage level comprises applying a power-supply voltage at a turn-on voltage level at least in the first period to respectively make the pre-pull-down node and the pull-down node at the turn-on voltage level to allow the pull-up node and the output terminal connected the reference voltage terminal fixed at the turn-off voltage level.

18. A display apparatus, comprising the GOA circuit of claim 10 .

19. A gate-driving unit circuit, comprising:

a first transistor having a gate electrode and a first electrode commonly coupled to an input terminal and a second electrode coupled to a pull-up node;

a second transistor having a gate electrode coupled to a reset signal terminal, a first electrode coupled to a reference voltage terminal, and a second electrode coupled to the pull-up node;

a third transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to a clock signal terminal, and a second electrode coupled to an output terminal;

a fourth transistor having a gate electrode coupled to the reset signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the output terminal;

a fifth transistor having a gate electrode and a first electrode coupled to a power-supply voltage terminal, and a second electrode coupled to a pre-pull-down node;

a sixth transistor having a gate electrode coupled to the pre-pull-down node, a first electrode coupled to the first electrode of the fifth transistor, and a second electrode coupled to a pull-down node;

a seventh transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pre-pull-down node;

an eighth transistor having a gate electrode coupled to the pull-up node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-down node;

a ninth transistor having a gate electrode coupled to the pull-down node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-up node;

a tenth transistor having a gate electrode coupled to the pull-down node, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the output terminal;

an eleventh transistor having a gate electrode coupled to the pre-pull-down signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pre-pull-down node;

a twelfth transistor having a gate electrode coupled to the pre-pull-down signal terminal, a first electrode coupled to the reference voltage terminal, and a second electrode coupled to the pull-down node; and

a storage capacitor having a first port coupled to the pull-up node and a second port coupled to the output terminal.