Memory device and method of operating the same
A memory device may include: memory cells each having any one of first and second programmed states as a target programmed state; a peripheral circuit configured to perform a program operation so that each memory cell has a threshold voltage corresponding to the target programmed state; and a control circuit configured to control the peripheral circuit. The control circuit may include a program operation controller configured to control the peripheral circuit so that, during the program operation, an intermediate program operation is performed on the memory cells using an intermediate verify voltage, an additional program operation is performed on memory cells each having the second programmed state as a target programmed state if an intermediate verify operation passes, and a final program operation is performed on the memory cells such that each memory cell has a threshold voltage corresponding to the target programmed state.
1. A method of operating a memory device configured to perform a program operation of storing data in memory cells, wherein the memory cells have any one program state among a first program state and a second program state as a target program state, respectively, wherein the first program state and the second program state are adjacent to each other among a plurality of program states, the method comprising:
performing an intermediate program operation by applying an intermediate program voltage to the memory cells to have threshold voltages corresponding to an intermediate program state;
performing, after the intermediate program operation, an additional program operation by applying an additional program voltage to memory cells which have the second program state as the target program state; and
performing, after the additional program operation, a final program operation for the memory cells to have the threshold voltages corresponding to the target program state, respectively,
wherein the performing the additional program operation comprises:
applying the additional program voltage to a word line commonly coupled to the memory cells; and
applying, while the additional program voltage is applied, a program inhibit voltage to bit lines coupled to memory cells which have the first program state as the target program state.
2. The method according to claim 1 ,
wherein the performing the additional program operation further comprises:
applying, while the additional program voltage is applied, a program enable voltage to bit lines coupled to memory cells which have the second program state as the target program state.
3. The method according to claim 1 , wherein the program operation includes a plurality of program loops and the additional program operation is performed in a next program loop after the intermediate program operation is performed.
4. The method according to claim 1 , wherein the additional program voltage is greater than the intermediate program voltage by a set step voltage.
5. The method according to claim 2 , wherein the program enable voltage is a ground voltage.
6. The method according to claim 2 , wherein the program inhibit voltage is a power supply voltage.
7. The method according to claim 1 , wherein the performing the intermediate program operation comprises:
applying the intermediate program voltage to a word line commonly coupled to the memory cells; and
applying at least one verify voltage to the word line.
8. The method according to claim 1 , wherein the program operation is performed in an incremental step pulse program (ISPP) manner.