Semiconductor device and method of manufacturing the same

1. A semiconductor device, comprising:

a first field effect transistor including at least two channel structure units each having a nanowire structure or a nanosheet structure; and

a second field effect transistor having a Fin structure,

wherein the channel structure units are spaced apart from each other in a thickness direction of the first field effect transistor, and

wherein 0.90≤H L /H H ≤1.04 is satisfied where a total height of the channel structure units is H L and a height of a channel formation region of the second field effect transistor is H H .

2. The semiconductor device according to claim 1 , wherein a gate insulating film and a gate electrode for the first field effect transistor are formed in the channel structure unit in the first field effect transistor, and

wherein a gate insulating film and a gate electrode for the second field effect transistor are formed in the channel formation region in the second field effect transistor.

3. The semiconductor device according to claim 1 , wherein the first field effect transistor is configured by a combination of an n-channel first field effect transistor and a p-channel first field effect transistor.

4. The semiconductor device according to claim 1 , wherein the second field effect transistor is configured by a combination of an n-channel second field effect transistor and a p-channel second field effect transistor.

5. The semiconductor device according to claim 1 , wherein the second field effect transistor includes an n-channel second field effect transistor.

6. The semiconductor device according to claim 1 , wherein the first field effect transistor is a low withstand voltage/field effect transistor, and wherein the second field effect transistor is a high withstand voltage/field effect transistor.

7. A semiconductor device, comprising:

a first field effect transistor including at least two channel structure units each having a nanowire structure or a nanosheet structure; and

a second field effect transistor having a Fin structure,

wherein the channel structure units are spaced apart from each other in a thickness direction of the first field effect transistor,

wherein the first field effect transistor is configured by a combination of an n-channel first field effect transistor and a p-channel first field effect transistor, and

wherein the channel structure unit in one of the n-channel first field effect transistor and the p-channel first field effect transistor is formed in an odd-numbered level of a layer, and the channel structure unit of another first field effect transistor is formed in an even-numbered level of a layer.

8. The semiconductor device according to claim 7 , wherein a gate insulating film and a gate electrode for the first field effect transistor are formed in the channel structure unit in the first field effect transistor, and wherein a gate insulating film and a gate electrode for the second field effect transistor are formed in the channel formation region in the second field effect transistor.

9. The semiconductor device according to claim 7 , wherein the channel structure unit in the n-channel first field effect transistor contains Si, and wherein the channel structure unit in the p-channel first field effect transistor contains SiGe.

10. The semiconductor device according to claim 7 , wherein the second field effect transistor is configured by a combination of an n-channel second field effect transistor and a p-channel second field effect transistor.

11. The semiconductor device according to claim 7 , wherein the second field effect transistor includes an n-channel second field effect transistor.

12. The semiconductor device according to claim 7 , wherein the first field effect transistor is a low withstand voltage/field effect transistor, and wherein the second field effect transistor is a high withstand voltage/field effect transistor.

13. A semiconductor device, comprising

a first field effect transistor including at least two channel structure units each having a nanowire structure or a nanosheet structure; and

a second field effect transistor having a Fin structure,

wherein the channel structure units are spaced apart from each other in a thickness direction of the first field effect transistor,

wherein the first field effect transistor is configured by a combination of an n-channel first field effect transistor and a p-channel first field effect transistor,

wherein the channel structure unit in the n-channel first field effect transistor contains Si, and

wherein the channel structure unit in the p-channel first field effect transistor contains SiGe.

14. The semiconductor device according to claim 13 , wherein the first field effect transistor is a low withstand voltage/field effect transistor, and wherein the second field effect transistor is a high withstand voltage/field effect transistor.

15. A semiconductor device, comprising

a first field effect transistor including at least two channel structure units each having a nanowire structure or a nanosheet structure; and

a second field effect transistor having a Fin structure,

wherein the channel structure units are spaced apart from each other in a thickness direction of the first field effect transistor,

wherein the second field effect transistor is configured by a combination of an n-channel second field effect transistor and a p-channel second field effect transistor,

wherein the channel formation region in the n-channel second field effect transistor contains Si, and

wherein the channel formation region in the p-channel second field effect transistor contains SiGe.

16. A semiconductor device, comprising

a first field effect transistor including at least two channel structure units each having a nanowire structure or a nanosheet structure; and

a second field effect transistor having a Fin structure,

wherein the channel structure units are spaced apart from each other in a thickness direction of the first field effect transistor,

wherein the first field effect transistor is a low withstand voltage/field effect transistor, and

wherein the second field effect transistor is a high withstand voltage/field effect transistor.

17. The semiconductor device according to claim 16 , wherein

a voltage applied to the gate electrode of the first field effect transistor is 0.5 to 0.8 volts, and

a voltage applied to the gate electrode of the second field effect transistor is 1.5 to 3 volts.

18. A method of manufacturing a semiconductor device, comprising the steps of:

(A) in a first region and a second region of a base, forming a first sacrificial layer on the first region and next forming a first semiconductor layer on the first sacrificial layer and on the second region;

(B) forming a second sacrificial layer on the first semiconductor layer in the first region and next forming a second semiconductor layer on the second sacrificial layer and on the first semiconductor layer in the second region;

(C) forming a stacked structure body including the first semiconductor layer, the first sacrificial layer, the second semiconductor layer, and the second sacrificial layer on the first region and next removing parts of the second sacrificial layer and the first sacrificial layer in the stacked structure body;

(C-1) obtaining a first structure including a source/drain region including the stacked structure body and a channel structure unit including the first semiconductor layer and the second semiconductor layer spaced apart from the first semiconductor layer in the first region; and

(C-2) obtaining a second structure including a source/drain region including a stacked structure of the first semiconductor layer and the second semiconductor layer, and a channel formation region in the second region; and

(D) forming a gate insulating film and a gate electrode in the channel structure unit in the first structure and in the channel formation region in the second structure, and therefore obtaining a first field effect transistor and a second field effect transistor in the first region and the second region, respectively.

19. A method of manufacturing a semiconductor device, comprising the steps of:

(A) forming a first semiconductor layer on a first region and on a second region of a base;

(B) forming a sacrificial layer on the first semiconductor layer, next removing the sacrificial layer in the second region, forming a second semiconductor layer on the sacrificial layer in the first region, and forming the second semiconductor layer on the first semiconductor layer in the second region;

(C) forming a stacked structure body including the second semiconductor layer, the sacrificial layer, the first semiconductor layer and next removing a part of the sacrificial layer in the stacked structure body in the first region;

(C-1) obtaining a first structure including a source/drain region including the stacked structure body and a channel structure unit including the first semiconductor layer and the second semiconductor layer spaced apart from the first semiconductor layer in the first region; and

(C-2) obtaining a second structure including a source/drain region including a stacked structure of the first semiconductor layer and the second semiconductor layer, and a channel formation region in the second region; and

(D) forming a gate insulating film and a gate electrode in the channel structure unit in the first structure and in the channel formation region in the second structure, and therefore obtaining a first field effect transistor and a second field effect transistor in the first region and the second region, respectively.

20. A method of manufacturing a semiconductor device, comprising the steps of:

(A) in a first a region, a first b region, a second a region, and a second b region of a base, forming a first A semiconductor layer on the first a region, the first b region, and the second a region and next forming a first B semiconductor layer on the first A semiconductor layer in the first a region and the first b region and on the second b region;

(B) forming a second A semiconductor layer on the first B semiconductor layer in the first a region and the first b region and on the first A semiconductor layer in the second a region and next forming a second B semiconductor layer on the second A semiconductor layer in the first a region and the first b region and on the first B semiconductor layer in the second b region;

(C) forming a first stacked structure body including the second B semiconductor layer, the second A semiconductor layer, the first B semiconductor layer, and the first A semiconductor layer in the first a region, and forming a second stacked structure body including the second B semiconductor layer, the second A semiconductor layer, the first B semiconductor layer, and the first A semiconductor layer in the first b region;

(D) removing parts of the second B semiconductor layer and the first B semiconductor layer in the first stacked structure body in the first a region, and removing parts of the second A semiconductor layer and the first A semiconductor layer in the second stacked structure body in the first b region;

(D-1) obtaining a first A structure including a source/drain region including the first stacked structure body and a channel structure unit including the first A semiconductor layer and the second A semiconductor layer spaced apart from the first A semiconductor layer in the first a region;

(D-2) obtaining a first B structure including a source/drain region including the second stacked structure body and a channel structure unit including the first B semiconductor layer and the second B semiconductor layer spaced apart from the first B semiconductor layer in the first b region;

(D-3) obtaining a second A structure including a source/drain region including a stacked structure of the first A semiconductor layer and the second A semiconductor layer and a channel formation region in the second a region;

(D-4) obtaining a second B structure including a source/drain region including a stacked structure of the first B semiconductor layer and the second B semiconductor layer and a channel formation region in the second b region; and

(E) forming a gate insulating film and a gate electrode in the channel structure units in the first A structure and the first B structure and in the channel formation regions in the second A structure and the second B structure, and therefore obtaining a first A field effect transistor, a first B field effect transistor, a second A field effect transistor, and a second B field effect transistor in the first a region, the first b region, the second a region, and the second b region of the base, respectively.