Ferroelectric memory devices with reduced edge leakage and methods for forming the same

1. A method for forming a ferroelectric memory cell, comprising:

forming a stack structure comprising a first electrode material layer, a second electrode material layer, and a ferroelectric material layer between the first electrode material layer and the second electric material layer;

performing an etching process on the stack structure to form a capacitor structure comprising a patterned first electrode material layer, a patterned second electrode material layer, and a ferroelectric layer between the patterned first electrode material layer and the patterned second electrode material layer; and

performing a recess etch, after the etching process, on at least one of the patterned first electrode material layer and the patterned second electrode layer to form the first electrode and the second electrode, wherein a recess is between a side surface of at least one of the first electrode or the second electrode and a side surface of the ferroelectric layer.

2. The method of claim 1 , wherein:

the first and second electrode material layers each comprises at least one of titanium nitride (TiN) or tantalum nitride (TaN); and

performing the etching process on the stack structure comprises etching the stack structure using an etchant gas comprising at least one of boron trichloride (BCl 3 ), chlorine (Cl 2 ), fluorine (F 2 ), carbon tetrafluoride (CF 4 ), carbon fluoride (CHF x ), sulfur fluoride (SF x ), nitrogen fluoride (NF x ), nitrogen (N 2 ), or argon (Ar).

3. The method of claim 1 , further comprising, for the etching process, using a mask layer over the stack stricture as an etch mask to:

pattern the first electrode material layer, the ferroelectric material layer, and the second electrode material layer to form, respectively, the patterned first electrode material layer, the ferroelectric layer, and the patterned second electrode material layer; and

perform a recess etch on the patterned first electrode material layer to form the first electrode and a respective recess between the side surface of the first electrode and the ferroelectric layer.

4. The method of claim 3 , wherein performing the recess etch comprises performing the recess etch on the patterned first electrode material layer, comprising at least one of:

performing a first recess etch during the patterning of the ferroelectric material layer; or

performing a second recess etch during the patterning of the second electrode material layer.

5. The method of claim 3 , wherein performing the recess etch comprises performing the recess etch on the patterned first electrode material layer, comprising:

after a formation of the patterned first electrode material layer, the ferroelectric layer, and the second electrode, trimming the mask layer such that a respective recess is formed between a side surface of the mask layer and the side surface of the patterned first electrode material layer; and

etching, using the trimmed mask layer as an etch mask, the patterned first electrode material layer to remove a portion of the patterned first electrode material layer exposed by the trimmed mask layer.

6. The method of claim 3 , wherein performing the recess etch comprises performing the recess etch on each of the patterned first and second electrode material layers at the same time to respectively form the first and second electrodes, wherein a respective recess is between a side surface of each of the first and second electrodes and the side surface of the ferroelectric layer.

7. The method of claim 1 , wherein the side surface of each of the first electrode and the second electrode comprises a respective top surface of the first electrode and the second electrode, and a side surface of the ferroelectric layer comprises a top surface of the ferroelectric layer, the second electrode, the ferroelectric layer, and the first electrode being disposed radially and outwardly; and wherein patterning the recess etch comprises:

planarizing top surfaces of the first electrode material layer, the second electrode material layer, and the ferroelectric material layer, and

etching a top portion of at least one of the first and second electrode material layers, the etching having a slower etch rate on the ferroelectric material layer than on the first and second electrode material layers.

8. A method for forming a ferroelectric memory cell, comprising:

forming a stack structure comprising a first electrode material layer, a second electrode material layer, and a ferroelectric material layer between the first electrode material layer and the second electric material layer;

patterning the stack structure, using a mask layer, to form a capacitor structure comprising a patterned first electrode material layer, a patterned second electrode material layer, and a ferroelectric layer between the patterned first electrode material layer and the patterned second electrode material layer; and

performing a recess etch, using the mask layer, on at least one of the patterned first electrode material layer and the patterned second electrode layer to form the first electrode and the second electrode, wherein a dimension of at least one of the first electrode or the second electrode is less than a dimension of the mask layer along an extending direction of the mask layer.

9. The method of claim 8 , wherein performing the recess etch comprises performing the recess etch, using the mask layer, on the patterned first electrode material layer, comprising at least one of:

performing a first recess etch during the patterning of the ferroelectric material layer; or

performing a second recess etch during the patterning of the second electrode material layer.

10. The method of claim 8 , wherein performing the recess etch, using the mask layer, comprises performing the recess etch on the patterned first electrode material layer, comprising:

performing the recess etch during the patterning of the second electrode material layer.

11. The method of claim 8 , wherein performing the recess etch, using the mask layer, comprises performing the recess etch on the patterned first electrode material layer, comprising:

after a formation of the patterned first electrode material layer, the ferroelectric layer, and the second electrode, trimming the mask layer such that a respective recess is formed between a side surface of the mask layer and the side surface of the patterned first electrode material layer; and

etching, using the trimmed mask layer as an etch mask, the patterned first electrode material layer to remove a portion of the patterned first electrode material layer exposed by the trimmed mask layer.

12. The method of claim 8 , wherein performing the recess etch, using the mask layer, comprises performing the recess etch on each of the patterned first and second electrode material layers at the same time to respectively form the first and second electrodes, wherein a respective recess is between a side surface of each of the first and second electrodes and the side surface of the ferroelectric layer.

13. The method of claim 8 , wherein the side surface of each of the first electrode and the second electrode comprises a respective top surface of the first electrode and the second electrode, and a side surface of the ferroelectric layer comprises a top surface of the ferroelectric layer, the second electrode, the ferroelectric layer, and the first electrode being disposed radially and outwardly; and wherein patterning the recess etch comprises:

planarizing top surfaces of the first electrode material layer, the second electrode material layer, and the ferroelectric material layer, and

retching a top portion of at least one of the first and second electrode material layers, the etching having a slower etch rate on the ferroelectric material layer than on the first and second electrode material layers.

14. A method for forming a ferroelectric memory cell, comprising:

forming a stack structure comprising a first electrode material layer, a second electrode material layer, and a ferroelectric material layer between the first electrode material layer and the second electric material layer;

patterning the stack structure to form a capacitor structure comprising a patterned first electrode material layer, a patterned second electrode material layer, and a ferroelectric layer between the patterned first electrode material layer and the patterned second electrode material layer; and

performing a recess etch on each of the patterned first electrode material layer and the patterned second electrode layer to form the first electrode and the second electrode, wherein a recess is between a side surface of at least one of the first electrode or the second electrode and a side surface of the ferroelectric layer.

15. The method of claim 14 , wherein patterning the stack structure comprises, using a mask layer over the stack structure as an etch mask:

patterning the first electrode material layer, the ferroelectric material layer, and the second electrode material layer to form, respectively, the patterned first electrode material layer, the ferroelectric layer, and the patterned second electrode material layer; and

performing a recess etch on the patterned first electrode material layer to form the first electrode and a respective recess between the side surface of the first electrode and the ferroelectric layer.

16. The method of claim 14 , wherein performing the recess etch comprises performing the recess etch on the patterned first electrode material layer, comprising at least one of:

performing a first recess etch during the patterning of the ferroelectric material layer; or

performing a second recess etch during the patterning of the second electrode material layer.

17. The method of claim 14 , wherein performing the recess etch comprises performing the recess etch on the patterned first electrode material layer, comprising:

performing the recess etch during the patterning of the second electrode material layer.

18. The method of claim 14 , wherein performing the recess etch comprises performing the recess etch on the patterned first electrode material layer, comprising:

after a formation of the patterned first electrode material layer, the ferroelectric layer, and the second electrode, trimming the mask layer such that a respective recess is formed between a side surface of the mask layer and the side surface of the patterned first electrode material layer; and

etching, using the trimmed mask layer as an etch mask, the patterned first electrode material layer to remove a portion of the patterned first electrode material layer exposed by the trimmed mask layer.

19. The method of claim 14 , wherein performing the recess etch comprises performing the recess etch on each of the patterned first and second electrode material layers at the same time to respectively form the first and second electrodes, wherein a respective recess is between a side surface of each of the first and second electrodes and the side surface of the ferroelectric layer.