Field effect transistor

1. A field effect transistor comprising:

a semiconductor layer;

a gate electrode provided on a channel region in the semiconductor layer; and

a channel adjusting member provided adjacent to the channel region on one surface of the semiconductor layer and overlapping the gate electrode on a plane, wherein

the channel adjusting member provides a depletion layer in the channel region,

the depletion layer is provided by a β-ray, and

at least a portion of the depletion layer is removed when a positive voltage is applied to the gate electrode.

2. The field effect transistor of claim 1 , wherein a channel is provided in the channel region when the positive voltage is applied to the gate electrode and the at least a portion of the depletion layer is removed.

3. The field effect transistor of claim 1 , wherein the depletion layer is provided by the β-ray, which is emitted from the channel adjusting member.

4. The field effect transistor of claim 1 , wherein the channel adjusting member is buried in the gate electrode and surrounded by the gate electrode.

5. The field effect transistor of claim 4 , further comprising an adjusting member insulation layer disposed between the channel adjusting member and the gate electrode to electrically insulate the channel adjusting member and the gate electrode from each other.

6. The field effect transistor of claim 1 , wherein the channel adjusting member overlaps the channel region in a substrate provided on a bottom surface of the semiconductor layer.

7. The field effect transistor of claim 1 , wherein the channel adjusting member and the gate electrode are sequentially laminated on the channel region.

8. The field effect transistor of claim 1 , wherein the channel adjusting member comprises a nickel isotope (Ni-63), tritium (H-3), a promethium isotope (Pm-147), or a strontium isotope (Sr-90).

9. The field effect transistor of claim 1 , further comprising a source electrode and a drain electrode, which are provided on the semiconductor layer and spaced apart from each other with the gate electrode therebetween.

10. The field effect transistor of claim 1 , wherein the semiconductor layer comprises a gallium nitride (GaN) layer and a gallium aluminum nitride (AlGaN) layer, which are sequentially laminated.

11. A field effect transistor comprising:

a semiconductor layer;

a source electrode and a drain electrode, which are spaced apart from each other on a top surface of the semiconductor layer;

a gate electrode disposed between the source electrode and the drain electrode on the top surface of the semiconductor layer;

a channel adjusting member buried in the gate electrode; and

a depletion layer provided in a channel region of the semiconductor layer, wherein

the channel adjusting member emits β-particles to the semiconductor layer, and

a portion of the depletion layer is removed by a positive voltage applied to the gate electrode.

12. The field effect transistor of claim 11 , wherein the depletion layer is provided in the channel region of the semiconductor layer by the β-particles.

13. The field effect transistor of claim 12 , wherein

a channel is provided in the channel region of the semiconductor layer.

14. The field effect transistor of claim 11 , further comprising an adjusting member insulation layer disposed between the channel adjusting member and the gate electrode to electrically insulate the channel adjusting member and the gate electrode from each other.

15. The field effect transistor of claim 11 , wherein the channel adjusting member comprises a nickel isotope (Ni-63), tritium (H-3), a promethium isotope (Pm-147), or a strontium isotope (Sr-90).

16. The field effect transistor of claim 11 , wherein the semiconductor layer comprises a gallium nitride (GaN) layer and a gallium aluminum nitride (AlGaN) layer, which are sequentially laminated.