Compensation circuit for delta-sigma modulators, corresponding device and method
A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.
1. A system, comprising:
an input interface, which, in operation, receives an analog input signal;
an output interface, which, in operation, outputs a delta-sigma modulated signal; and
a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including:
a first integrator;
an analog-to-digital converter coupled to the output interface;
a feedback-loop coupled between an input of the first integrator and the output interface;
a second integrator coupled between the first integrator and the analog-to-digital converter; and
loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal, wherein
the loop-delay compensation circuitry includes a derivative circuit coupled between an output of the first integrator and the plurality of switches;
the feedback-loop includes:
a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator; and
a first digital-to-analog converter coupled between the output interface and a second input of the first adder; and
the delta-sigma modulation circuit includes:
a second adder having a first input coupled to an output of the first integrator, a second input coupled to an output of the loop-delay compensation circuitry, and an output coupled to the second integrator; and
a third adder having a first input coupled to an output of the first integrator, a second input coupled to an output of the second integrator and an output coupled to the analog-to-digital converter.
2. The system of claim 1 wherein,
the first digital-to-analog converter, in operation, generates a first weighted feedback signal.
3. The system of claim 1 wherein the delta-sigma modulation circuit comprises an inverter coupled between the output of the first integrator and the first input of the third adder.
4. A system, comprising:
an input interface, which, in operation, receives an analog input signal;
an output interface, which, in operation, outputs a delta-sigma modulated signal; and
a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including:
a first integrator;
an analog-to-digital converter coupled to the output interface;
a feedback-loop coupled between an input of the first integrator and the output interface;
a second integrator coupled between the first integrator and the analog-to-digital converter; and
loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal, wherein
the loop-delay compensation circuitry includes a derivative circuit coupled between an output of the first integrator and the plurality of switches; and
the loop-delay compensation circuitry comprises a third integrator coupled to an output of the plurality of switches.
5. The system of claim 4 wherein,
the feedback-loop includes:
a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator;
a first digital-to-analog converter coupled between the output interface and a second input of the first adder;
a second adder having a first input coupled to an output of the first integrator and an output coupled to an input of the second integrator; and
a second digital-to-analog converter coupled between the output interface and a second input of the second adder; and
the loop-delay compensation circuitry comprises a third adder having a first input coupled to an output of the second integrator, a second input coupled to an output of the third integrator and an output coupled to the analog-to-digital converter.
6. The system of claim 5 wherein,
the first digital-to-analog converter, in operation, generates a first weighted feedback signal; and
the second digital-to-analog converter, in operation, generates a second weighted feedback signal.
7. The system of claim 4 wherein,
the feedback-loop includes:
a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator; and
a first digital-to-analog converter coupled between the output interface and a second input of the first adder; and
the loop-delay compensation circuitry comprises a second adder having a first input coupled to an output of the second integrator, a second input coupled to an output of the third integrator and an output coupled to the analog-to-digital converter.
8. The system of claim 7 wherein,
the first digital-to-analog converter, in operation, generates a first weighted feedback signal.
9. The system of claim 7 wherein,
the delta-sigma modulation circuit includes a third adder coupled between the output of the second integrator and the second adder, the third adder having a first input coupled to an output of the first integrator, a second input coupled to the output of the second integrator and an output coupled to the first input of the second adder.
10. The system of claim 9 wherein the delta-sigma modulation circuit comprises an inverter coupled between the output of the first integrator and the first input of the third adder.
11. The system of claim 4 wherein,
the feedback-loop includes:
a first adder having a first input coupled to the input interface and an output coupled to an input of the first integrator;
a first digital-to-analog converter coupled between the output interface and a second input of the first adder;
a second adder having a first input coupled to an output of the first integrator and an output coupled to an input of the second integrator; and
a second digital-to-analog converter coupled between the output interface and a second input of the second adder; and
an output of the loop-delay compensation circuitry is coupled to a third input of the second adder.
12. The system of claim 11 wherein,
the first digital-to-analog converter, in operation, generates a first weighted feedback signal; and
the second digital-to-analog converter, in operation, generates a second weighted feedback signal.
13. A system, comprising:
an input interface, which, in operation, receives an analog input signal;
an output interface, which, in operation, outputs a delta-sigma modulated signal; and
a delta-sigma modulation circuit having a sampling period and coupled between the input interface and the output interface, wherein the delta-sigma modulation circuit, in operation, generates the delta-sigma modulated signal based on the analog input signal, the delta-sigma modulation circuit including:
a first integrator;
an analog-to-digital converter coupled to the output interface;
a feedback-loop coupled between an input of the first integrator and the output interface;
a second integrator coupled between the first integrator and the analog-to-digital converter; and
loop-delay compensation circuitry having a plurality of switches, wherein the loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal, wherein
the first integrator comprises a first differential amplifier; and
the second integrator comprises a second differential amplifier.
14. The system of claim 13 , wherein the first differential amplifier has differential input node terminals and differential output node terminals with resistor/capacitor (RC) feedback networks coupled between the differential output node terminals and the differential input node terminals.
15. The system of claim 14 , wherein
the second differential amplifier has differential input node terminals and differential output node terminals with RC feedback networks coupled between the differential output node terminals and the differential input node terminals, wherein the RC feedback networks of the second differential amplifier, in operation, provide virtual ground nodes; and
the differential output node terminals of the first differential amplifier are coupled to the virtual ground nodes of the second differential amplifier via respective capacitances and switches of the plurality of switching circuits.