IP Library Granted Patent US 11,296,211
Granted Patent B2
US 11,296,211 · App. 16/910,833 · Granted Apr 5, 2022

Method for preparing semiconductor device with annular semiconductor fin

Inventor: Te-Yin Chen (Taoyuan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L29/66666H01L21/027H01L21/823431H01L29/41791H01L29/66795H01L29/785H01L29/7827
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Quick Facts
Patent No.
US 11,296,211
App. No.
16/910,833
Granted
Apr 5, 2022
Kind
B2
Abstract

A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.

Claims (18)

1. A method for preparing a semiconductor device, comprising:

forming a ring structure over a semiconductor substrate;

etching the semiconductor substrate by using the ring structure as a mask to form an annular vertical fin;

forming an inner spacer on an inner sidewall of the annular vertical fin and an outer spacer on an outer sidewall of the annular vertical fin;

etching the semiconductor substrate by using the ring structure, the inner spacer and the outer spacer as a mask to form a first recess within the annular vertical fin and a second recess surrounding the annular vertical fin;

epitaxially growing a first bottom source/drain structure in the first recess and a second bottom source/drain structure in the second recess;

forming a first silicide layer to cover the first bottom source/drain structure and a second silicide layer to cover and surround the second bottom source/drain structure;

forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer;

epitaxially growing a top source/drain structure over the annular vertical fin; and

implanting dopants into a top surface of the semiconductor substrate exposed by the annular vertical fin to form a processed area before the inner spacer and the outer spacer are formed, wherein the processed area is etched during the formation of the first recess and the second recess, and the first recess and the second recess expose sidewalls of the processed area;

wherein the first bottom source/drain structure and the second bottom source/drain structure are in direct contact with the processed area.

2. The method for preparing a semiconductor device of claim 1 , further comprising:

removing the inner spacer and the outer spacer after the first silicide layer and the second silicide layer are formed; and

forming a bottom spacer layer to cover the first silicide layer and the second silicide layer before the first gate structure and the second gate structure are formed.

3. The method for preparing a semiconductor device of claim 2 , wherein a top surface of the first silicide layer and a top surface of the second silicide layer are higher than a bottom surface of the bottom spacer layer.

4. The method for preparing a semiconductor device of claim 1 , further comprising:

forming a top spacer layer to cover the first gate structure and the second gate structure before the top source/drain structure is epitaxially grown, wherein the top spacer layer is in direct contact with sidewalls of the ring structure; and

removing the ring structure and a portion of the top spacer layer to expose a top surface and a sidewall of the annular vertical fin before the top source/drain structure is epitaxially grown.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2020
From: CHEN, TE-YIN
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 053041/0540 →
Continuity (1)
Related Publication 20210408267A1 · Dec 30, 2021
Cited By (1)
US 12,615,840