Vertical thin film transistors having self-aligned contacts
Thin film transistors are described. An integrated circuit structure includes a first source or drain contact above a substrate. A gate stack pedestal is on the first source or drain contact, the gate stack pedestal including a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer. A channel material layer is over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact. Dielectric spacers are adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal. A second source or drain contact is over a portion of the channel material layer over the gate stack pedestal.
1. An integrated circuit structure, comprising:
a first source or drain contact above a substrate;
a gate stack pedestal on the first source or drain contact, the gate stack pedestal comprising a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer;
a channel material layer over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact;
dielectric spacers adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal; and
a second source or drain contact over a portion of the channel material layer over the gate stack pedestal.
2. The integrated circuit structure of claim 1 , wherein the dielectric spacers comprise silicon nitride or silicon oxynitride.
3. The integrated circuit structure of claim 1 , wherein channel material layer comprises a semiconducting oxide material.
4. The integrated circuit structure of claim 1 , wherein channel material layer comprises polycrystalline silicon.
5. The integrated circuit structure of claim 1 , wherein the gate dielectric sidewalls have a thickness less than a thickness of the first gate dielectric layer, and less than a thickness of the second gate dielectric layer.
6. The integrated circuit structure of claim 1 , wherein the first gate dielectric layer, the second gate dielectric layer and the gate dielectric sidewalls are composed of a same material.
7. The integrated circuit structure of claim 1 , wherein the first gate dielectric layer and the gate dielectric sidewalls are composed of a different material.
8. The integrated circuit structure of claim 7 , wherein the second gate dielectric layer is composed of a different material than the first gate dielectric layer and the gate dielectric sidewalls.
9. The integrated circuit structure of claim 1 , wherein the second source or drain contact is on at least a portion of the dielectric spacers.
10. The integrated circuit structure of claim 1 , wherein the second source or drain contact is horizontally offset relative to the gate stack pedestal.
11. A method of fabricating an integrated circuit structure, the method comprising:
forming a first source or drain contact above a substrate;
forming a gate stack pedestal on the first source or drain contact, the gate stack pedestal comprising a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer;
forming a channel material over and along sidewalls of the gate stack pedestal, the channel material further on the first source or drain contact;
forming dielectric spacers adjacent portions of the channel material along the sidewalls of the gate stack pedestal and on a portion of the channel material on the first source or drain contact;
patterning the channel material on the first source or drain contact to form a channel material layer using the dielectric spacers as a mask; and
forming a second source or drain contact over a portion of the channel material layer over the gate stack pedestal by etching a conductive layer, wherein the dielectric spacers are an etch stop during the etching.
12. The method of claim 11 , wherein the dielectric spacers comprise silicon nitride or silicon oxynitride.
13. The method of claim 11 , wherein channel material layer comprises a semiconducting oxide material.
14. The method of claim 11 , wherein channel material layer comprises polycrystalline silicon.
15. An integrated circuit structure, comprising:
a first source or drain contact above a substrate;
a gate stack pedestal on the first source or drain contact, the gate stack pedestal comprising a first gate dielectric layer, a gate electrode layer on the first gate dielectric layer, a second gate dielectric layer on the gate electrode layer, and gate dielectric sidewalls along the first gate dielectric layer, the gate electrode layer and the second gate dielectric layer;
a channel material layer over and along sidewalls of the gate stack pedestal, the channel material layer further on a portion of the first source or drain contact;
first dielectric spacers adjacent portions of the channel material layer along the sidewalls of the gate stack pedestal, wherein the first dielectric spacers are passivating for the channel material layer;
second dielectric spacers adjacent the first dielectric spacers, wherein the second dielectric spacers have a higher etch resistance than the first dielectric spacers;
a second source or drain contact over a portion of the channel material layer over the gate stack pedestal.
16. The integrated circuit structure of claim 15 , wherein the first dielectric spacers comprise a dopant species.
17. The integrated circuit structure of claim 15 , wherein channel material layer comprises a semiconducting oxide material.
18. The integrated circuit structure of claim 15 , wherein channel material layer comprises polycrystalline silicon.
19. The integrated circuit structure of claim 15 , wherein the second source or drain contact is on at least a portion of the first and second dielectric spacers.
20. The integrated circuit structure of claim 15 , wherein the second source or drain contact is horizontally offset relative to the gate stack pedestal.