Memory device based on multi-bit perpendicular magnetic tunnel junction
Disclosed is a memory device including a multi-bit perpendicular magnetic tunnel junction, wherein the multi-bit perpendicular magnetic tunnel junction includes an upper synthetic antiferromagnetic layer, pinned layer, lower dual free layer, and upper free layer formed in a laminated manner between a top electrode and a bottom electrode.
1. A multi-bit perpendicular magnetic tunnel junction, comprising a first magnetic layer, a second magnetic layer, a third magnetic layer, and a fourth magnetic layer formed in a laminated manner between a top electrode and a bottom electrode,
wherein the first magnetic layer includes a lower synthetic antiferromagnetic layer, the second magnetic layer includes an upper synthetic antiferromagnetic layer, a bridge layer, and a pinned layer, the third magnetic layer includes a lower dual free layer, and the fourth magnetic layer includes an upper free layer,
wherein magnetization directions of the first magnetic layer and the second magnetic layer are fixed,
wherein the multi-bit perpendicular magnetic tunnel junction exhibits one resistance state among first to fourth resistance states depending on magnetization directions of the third magnetic layer and the fourth magnetic layer.
2. The multi-bit perpendicular magnetic tunnel junction according to claim 1 , wherein the first resistance state appears when magnetization directions of the upper synthetic antiferromagnetic layer and the pinned layer are parallel to a magnetization direction of the lower dual free layer, and the magnetization directions of the lower dual free layer and the upper free layer are parallel to each other.
3. The multi-bit perpendicular magnetic tunnel junction according to claim 1 , wherein the second resistance state appears when magnetization directions of the upper synthetic antiferromagnetic layer and the pinned layer are anti-parallel to a magnetization direction of the lower dual free layer, and the magnetization directions of the lower dual free layer and the upper free layer are parallel to each other,
the third resistance state appears when the magnetization directions of the upper synthetic antiferromagnetic layer and the pinned layer are parallel to the magnetization direction of the lower dual free layer, and the magnetization directions of the lower dual free layer and the upper free layer are anti-parallel to each other, and
the fourth resistance state appears when the magnetization directions of the upper synthetic antiferromagnetic layer and the pinned layer are anti-parallel to the magnetization direction of the lower dual free layer, and the magnetization directions of the lower dual free layer and the upper free layer are anti-parallel to each other.
4. The multi-bit perpendicular magnetic tunnel junction according to claim 1 , wherein, when a magnitude of a magnetic field applied from outside is swept in a range of a predetermined first threshold value to a predetermined second threshold value, the one resistance state is sequentially switched in an order of the second resistance state, the fourth resistance state, the first resistance state, and the third resistance state.
5. The multi-bit perpendicular magnetic tunnel junction according to claim 1 , further comprising:
a lower tunnel barrier layer formed between the pinned layer and the lower dual free layer; and
an upper tunnel barrier layer formed between the lower dual free layer and the upper free layer.
6. The multi-bit perpendicular magnetic tunnel junction according to claim 1 , wherein the lower dual free layer comprises a first lower free layer, an upper spacing layer, and a second lower free layer formed in the laminated manner.
7. The multi-bit perpendicular magnetic tunnel junction according to claim 1 , further comprising:
a lower spacing layer formed between the lower and upper synthetic antiferromagnetic layers.
8. A multi-bit perpendicular magnetic tunnel junction, comprising a first magnetic layer, a second magnetic layer, a third magnetic layer, and a fourth magnetic layer formed in a laminated manner between a top electrode and a bottom electrode,
wherein the first magnetic layer includes a lower synthetic antiferromagnetic layer, the second magnetic layer includes an upper synthetic antiferromagnetic layer, a lower bridge layer, and a pinned layer, the third magnetic layer includes a lower dual free layer, and the fourth magnetic layer includes an upper multiple free layer,
wherein magnetization directions of the first magnetic layer and the second magnetic layer are fixed,
wherein the multi-bit perpendicular magnetic tunnel junction exhibits one resistance state among first to fourth resistance states depending on magnetization directions of the third magnetic layer and the fourth magnetic layer.
9. The multi-bit perpendicular magnetic tunnel junction according to claim 8 , wherein the first resistance state appears when magnetization directions of the upper synthetic antiferromagnetic layer and the pinned layer are parallel to a magnetization direction of the lower dual free layer, and the magnetization directions of the lower dual free layer and the upper multiple free layer are parallel to each other.
10. The multi-bit perpendicular magnetic tunnel junction according to claim 8 , wherein the second resistance state appears when magnetization directions of the upper synthetic antiferromagnetic layer and the pinned layer are parallel to a magnetization direction of the lower dual free layer, and the magnetization directions of the lower dual free layer and the upper multiple free layer are anti-parallel to each other,
the third resistance state appears when the magnetization directions of the upper synthetic antiferromagnetic layer and the pinned layer are anti-parallel to the magnetization direction of the lower dual free layer, and the magnetization directions of the lower dual free layer and the upper multiple free layer are parallel to each other, and
the fourth resistance state appears when the magnetization directions of the upper synthetic antiferromagnetic layer and the pinned layer are anti-parallel to the magnetization direction of the lower dual free layer, and the magnetization directions of the lower dual free layer and the upper multiple free layer are anti-parallel to each other.
11. The multi-bit perpendicular magnetic tunnel junction according to claim 8 , wherein, when a magnitude of a magnetic field applied from outside is swept in a range of a predetermined first threshold value to a predetermined second threshold value, the one resistance state is sequentially switched in an order of the third resistance state, the second resistance state, the first resistance state, and the fourth resistance state.
12. The multi-bit perpendicular magnetic tunnel junction according to claim 8 , further comprising:
a lower tunnel barrier layer formed between the pinned layer and the lower dual free layer; and
an upper tunnel barrier layer formed between the lower dual free layer and the upper multiple free layer.
13. The multi-bit perpendicular magnetic tunnel junction according to claim 8 , wherein the upper multiple free layer comprises a first upper free layer, an upper bridge layer, and a second upper free layer formed in the laminated manner, and
the second upper free layer is formed in a multilayer structure in which a cobalt (Co) layer and a platinum (Pt) layer are alternately stacked.