Electrostatic discharge protection circuit
View Patent ↗An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.
1. A circuit comprising:
an electrostatic discharge clamp between a first rail and a second rail;
a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, wherein the trigger device receives a trigger signal as a first input and a second virtual power rail as a second input, wherein the trigger signal is connected to a first node, and wherein the second virtual power rail is connected to a second node; and
a charge dissipation element between the first node and the second rail to dissipate a residual charge at the first node, wherein the charge dissipation element comprises one of a single reverse diode, a single NMOS diode, or a single PMOS diode.
2. The circuit of claim 1 , further comprising a resistor-capacitor filter, the resistor-capacitor filter comprising a resistor and a capacitor, wherein the resistor is connected between the first node and the second node, and wherein the capacitor is connected between the first node and the second rail in parallel with the charge dissipation element.
3. The circuit of claim 2 , wherein electrostatic discharge clamp is connected to a first virtual power rail, and wherein the first virtual power is connected to the first rail via a first diode.
4. The circuit of claim 3 , wherein the second virtual power rail is connected to the first rail via a second diode, wherein the second diode is connected to the second node.
5. The circuit of claim 1 , wherein the trigger device is a buffer inverter.
6. The circuit of claim 1 , wherein the electrostatic discharge clamp is an NMOS transistor.
7. The circuit of claim 1 , wherein the trigger device is a buffer.
8. The circuit of claim 1 , wherein the electrostatic discharge clamp is a transistor comprising a first terminal connected to the first virtual power rail a second terminal connected to the second rail, and a third terminal connected to the trigger device.
9. A circuit comprising:
a first virtual power rail connected to a first rail via a first diode;
a second virtual power rail connected to the first rail via a second diode, wherein the second virtual power rail is connected to a second node;
an electrostatic discharge clamp connected between the first virtual power rail and a second rail;
a trigger device connected to the electrostatic discharge clamp and configured to activate the electrostatic discharge clamp during an electrostatic discharge event based upon a voltage level of the second virtual power rail and the voltage level of a trigger signal, wherein the trigger signal is connected to a first node; and
a charge dissipation element connected between the second rail and the second node to dissipate residual charge from the second node, wherein the charge dissipation element comprises one of a single reverse diode, a single NMOS diode, or a single PMOS diode.
10. The circuit of claim 9 , wherein the second virtual power rail is not connected to the electrostatic discharge.
11. The circuit of claim 10 , further comprising a resistor-capacitor filter, wherein a resistor of the resistor-capacitor filter is connected to the second diode, wherein the second virtual power rail is connected to the second node that is between the second diode and the resistor, and wherein the first node is between the resistor and a capacitor of the resistor-capacitor filter, the capacitor being connected between the second rail and the first node.
12. The circuit of claim 9 , wherein the electrostatic discharge clamp is an NMOS transistor.
13. The circuit of claim 9 , wherein the trigger device is a buffer.
14. The circuit of claim 9 , wherein the trigger device is a buffer inverter.
15. A method comprising:
connecting an electrostatic discharge clamp between a first rail and a second rail;
connecting a trigger device to the electrostatic discharge clamp, wherein the trigger device receives a trigger signal as a first input and a second virtual power rail as a second input, wherein the trigger signal is connected to a first node, and wherein the second virtual power rail is connected to a second node;
connecting a charge dissipation element between the first node and the second rail, wherein the charge dissipation element comprises one of a single reverse diode, a single NMOS diode, or a single PMOS diode;
dissipating a residual charge by the charge dissipation element from the first node to the second rail;
varying an output of the trigger device in response to an electrostatic discharge event to activate the electrostatic discharge clamp; and
diverting electrostatic discharge current by the electrostatic discharge clamp from the first rail to the second rail in response to the activation.
16. The method of claim 15 , further comprising:
varying the output of the trigger device after the electrostatic discharge event to deactivate the electrostatic discharge clamp until a next electrostatic discharge event; and
continuing to dissipate the residual charge by the charge dissipation element from the input of the trigger device to the second rail.
17. The method of claim 15 , wherein the trigger device is a buffer inverter.
18. The method of claim 15 , wherein the electrostatic discharge clamp is an NMOS transistor.
19. The method of claim 15 , wherein the trigger device is a buffer.
20. The method of claim 15 , further comprising connecting the electrostatic discharge clamp between a first virtual power rail and the second rail, wherein the first virtual power rail is connected to the first rail via a first diode.