Phase-aligning multiple synthesizers
Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.
1. A synthesizer system comprising:
a plurality of synthesizer circuits coupled to receive a common reference signal, each synthesizer circuit comprising:
a synthesizer having an input coupled to receive the common reference signal and an output derived from the common reference signal;
a measurement circuit comprising a time-to-digital converter having a first input coupled to receive the common reference signal, a second input coupled to the output of the synthesizer, and an output for providing one or more time measurement values, each time measurement value representing a time difference between a first event of the common reference signal on the first input and a subsequent second event of the synthesizer output on the second input; and
a synchronization circuit configured to phase-adjust, independently of the other synthesizers, the synthesizer output relative to the common reference signal input by a phase adjustment amount equivalent to a determined time difference between the synthesizer output and the common reference signal input based on the one or more time measurement values to phase-align the synthesizer output with the other synthesizer outputs without any coordination between the synchronization circuits.
2. A system according to claim 1 , wherein the first event of the common reference signal is a rising clock edge of the common reference signal and the subsequent second event of the synthesizer output is a subsequent rising clock edge of the synthesizer output.
3. A system according to claim 1 , wherein the synthesizer comprises a phase-locked loop.
4. A system according to claim 3 , wherein the synchronization circuit comprises a delta sigma modulator of the phase-locked loop.
5. A system according to claim 1 , wherein the synchronization circuit comprises a delay circuit.
6. A system according to claim 5 , wherein the delay circuit comprises delay lines.
7. A system according to claim 1 , further comprising:
a controller configured to determine a phase adjustment value for a given synthesizer circuit based on one or more measurement values from the given synthesizer circuit.
8. A system according to claim 7 , wherein the controller is part of the given synthesizer circuit.
9. A system according to claim 7 , wherein the controller is external to the given synthesizer circuit.
10. A system according to claim 7 , wherein the phase adjustment value comprises a negative time value.
11. A system according to claim 7 , wherein the phase adjustment value comprises a phase offset.
12. A system according to claim 7 , wherein the phase adjustment value is based on a plurality of measurement values.
13. A system according to claim 12 , wherein the phase adjustment value comprises an average of the plurality of measurement values.
14. A system according to claim 7 , wherein the controller is configured to provide the phase adjustment value to a phase modulation port of the synthesizer.
15. A system according to claim 1 , wherein the common reference signal is an alternating clock signal.
16. A system according to claim 1 , further comprising:
a circuit configured to provide the common reference signal.
17. A method of phase aligning multiple synthesizers, the method comprising:
providing a common reference signal to each of a plurality of synthesizers; and
for each synthesizer:
providing, using a time-to-digital converter, one or more time measurement values, each time measurement value representing a time difference between a first event of the common reference signal and a subsequent second event of the synthesizer output; and
phase-adjusting, independently of the other synthesizers, the synthesizer output relative to the common reference signal input by a phase adjustment amount equivalent to a determined time difference between the synthesizer output and the common reference signal input based on the one or more time measurement values to phase-align the synthesizer output with the other synthesizer outputs.
18. A method according to claim 17 , wherein phase-adjusting operation of the synthesizer based on the one or more measurement values comprises:
determining a phase adjustment value for the synthesizer based on one or more measurement values from the synthesizer.
19. A method according to claim 18 , wherein the phase adjustment value is one of (a) a negative time value or (b) a phase offset.
20. A system according to claim 1 , wherein the first event starts a counter of the time-to-digital converter and the subsequent second event stops the counter of the time-to-digital converter.