Power savings in processors
A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.
1. A method comprising:
generating, via a processing system, gate-level activity information of a software-programmable processor design for all possible executions of a target application for any possible inputs to the target application to identify parts of the software-programmable processor design that are not exercised by the target application; and
performing, via the processing system, a constrained timing analysis on the software-programmable processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the software-programmable processor design such that parts of the software-programmable processor design that are exercised by the target application are guaranteed to meet timing constraints of the software-programmable processor design while parts of the software-programmable processor design that are not exercised by the target application are allowed to violate the timing constraints.
2. The method of claim 1 , wherein generating the gate-level activity information comprises performing symbolic simulation to identify unexercisable gates of the software-programmable processor design.
3. The method of claim 2 , wherein performing symbolic simulation comprises:
initializing a list of unexercisable gates as all gates of the software-programmable processor design;
initializing all inputs of the processor design to Xs, where each X represents an unknown logic value;
simulating the target application on the software-programmable processor design; and
removing each gate that toggles and each gate through which an X propagates during the simulation from the list of unexercisable gates.
4. The method of claim 1 , wherein performing the constrained timing analysis comprises:
identifying exercisable paths based on the gate-level activity information; and
performing a voltage safety analysis on each exercisable path to determine the minimum voltage at which the exercisable paths meet timing constraints.
5. The method of claim 4 , wherein performing the voltage safety analysis comprises performing the voltage safety analysis for worst case timing conditions.
6. The method of claim 4 , wherein performing the voltage safety analysis comprises lowering the voltage in steps and performing constrained timing analysis at each step to determine the lowest voltage at which the exercisable paths meet timing constraints.
7. The method of claim 1 , further comprising:
sizing an energy harvester for the software-programmable processor design based on the minimum operating voltage.
8. The method of claim 1 , further comprising:
sizing an energy storage device for the software-programmable processor design based on the minimum operating voltage.
9. A system comprising:
a non-transitory machine readable storage medium storing instructions; and
a processor to execute the instructions to:
generate gate-level activity information of a software-programmable processor design for all possible executions of a target application for any possible inputs to the target application to identify parts of the software-programmable processor design that are not exercised by the target application; and
perform a constrained timing analysis on the software-programmable processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the software-programmable processor design such that parts of the software-programmable processor design that are exercised by the target application are guaranteed to meet timing constraints of the software-programmable processor design while parts of the software-programmable processor design that are not exercised by the target application are allowed to violate the timing constraints.
10. The system of claim 9 , wherein the processor is to execute the instructions to generate the gate-level activity information by performing symbolic simulation to identify unexercisable gates of the software-programmable processor design.
11. The system of claim 10 , wherein the processor is to execute the instructions to perform symbolic simulation by:
initializing a list of unexercisable gates as all gates of the software-programmable processor design;
initializing all inputs of the software-programmable processor design to Xs, where each X represents an unknown logic value;
simulating the target application on the software-programmable processor design; and
removing each gate that toggles and each gate through which an X propagates during the simulation from the list of unexercisable gates.
12. The system of claim 9 , wherein the processor is to execute the instructions to perform the constrained timing analysis by:
identifying exercisable paths based on the gate-level activity information; and
performing a voltage safety analysis on each exercisable path to determine the minimum voltage at which the exercisable paths meet timing constraints.
13. The system of claim 12 , wherein the processor is to execute the instructions to perform the voltage safety analysis by performing the voltage safety analysis for worst case timing conditions.
14. The system of claim 12 , wherein the processor is to execute the instructions to perform the voltage safety analysis by lowering the voltage in steps and performing constrained timing analysis at each step to determine the lowest voltage at which the exercisable paths meet timing constraints.
15. The system of claim 9 , wherein the processor is to execute the instructions to further size an energy harvester for the software-programmable processor design based on the minimum operating voltage.
16. The system of claim 9 , wherein the processor is to execute the instructions to further size an energy storage device for the software-programmable processor design based on the minimum operating voltage.
17. A method comprising:
receiving, via a processing system, an application binary for a target application;
analyzing, via the processing system, the application binary to determine parts of a software-programmable processor design that cannot be exercised by the application binary and parts of the software-programmable processor design that can be exercised by the application binary; and
performing, via the processing system, a constrained timing analysis on the software-based processor design based on the parts of the software-programmable processor design that can be exercised by the application binary to determine the minimum operating voltage for executing the application binary on the software-programmable processor design.
18. The method of claim 17 , wherein analyzing the application binary comprises evaluating a control flow graph (CFG) of the application binary symbolically on the software-programmable processor design to determine which logic of the software-programmable processor design the application binary could toggle and which logic of the software-programmable processor design the application binary could never toggle.
19. The method of claim 17 , wherein performing the constrained timing analysis comprises performing the constrained timing analysis for worst case timing conditions such that the minimum operating voltage is guaranteed to be safe independent of process, voltage, and temperature variations.
20. The method of claim 17 , wherein the parts of the software-programmable processor design that cannot be exercised by the application binary are allowed to violate timing constraints of the software-programmable processor design.