Partial write management in a multi-tiled compute engine
Embodiments described herein provide a general purpose graphics processor comprising a plurality of tiles, each tile of the plurality of tiles comprising at least one execution unit, a local cache, and a cache control unit, and a high bandwidth memory communicatively coupled to the plurality of tiles, wherein the high bandwidth memory is shared between the plurality of tiles. The cache control unit is to implement a partial write management protocol to receive a partial write operation directed to a cache line in the local cache, the partial write operation comprising write data, write the data associated with the partial write operation to the local cache when the cache line is in a modified state, and forward the write data associated with the partial write operation to the high bandwidth memory when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state. Other embodiments may be described and claimed.
1. An apparatus, comprising:
a plurality of tiles, each tile of the plurality of tiles comprising at least one processing resource, a local cache, and a cache control unit; and
a high bandwidth memory communicatively coupled to the plurality of tiles, wherein the high bandwidth memory is shared between the plurality of tiles;
a processor to:
receive a partial write operation directed to a cache line in the local cache, the partial write operation comprising write data;
write the write data associated with the partial write operation to the local cache when the cache line is in a modified state; and
forward the write data associated with the partial write operation to the high bandwidth memory when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state.
2. The apparatus of claim 1 , the processor to:
implement a write through cache operation when the cache line is in an exclusive state.
3. The apparatus of claim 2 , the processor to:
disable a partial write management protocol in response to detecting a partial write disable state flag.
4. The apparatus of claim 3 , wherein the partial write disable state flag is set by a compute state command.
5. The apparatus of claim 3 , wherein the partial write disable state flag is set by an application via an input to an application programming interface (API).
6. The apparatus of claim 5 , the processor to:
disable the partial write management protocol for 256 byte blocks of cache in response to the partial write disable flag.
7. The apparatus of claim 6 , the processor to:
disable compression operations for the local cache.
8. A computer-implemented method, comprising:
receiving, in a processor of a tile in a graphics processor comprising a plurality of tiles, a partial write operation directed to a cache line in a local cache of the tile, the partial write operation comprising write data;
writing the write data associated with the partial write operation to the local cache when the cache line is in a modified state; and
forwarding the write data associated with the partial write operation to a high bandwidth memory communicatively coupled to the plurality of tiles when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state.
9. The computer-implemented method of claim 8 , further comprising:
implementing a write through cache operation when the cache line is in an exclusive state.
10. The computer-implemented method of claim 9 , further comprising:
disabling a partial write management protocol in response to detecting a partial write disable state flag.
11. The computer-implemented method of claim 10 , wherein the partial write disable state flag is set by a compute state command.
12. The computer-implemented method of claim 10 , wherein the partial write disable state flag is set by an application via an input to an application programming interface (API).
13. The computer-implemented method of claim 12 , further comprising:
disabling the partial write management protocol for 256 byte blocks of cache in response to the partial write disable flag.
14. The computer-implemented method of claim 13 , further comprising:
disabling compression operations for the local cache.
15. A non-transitory computer-readable medium comprising instructions which, when executed by a processor, configure the processor to:
receive, in a processor of a tile in a graphics processor comprising a plurality of tiles, a partial write operation directed to a cache line in a local cache of the tile, the partial write operation comprising write data;
write the write data associated with the partial write operation to the local cache when the cache line is in a modified state; and
forward the write data associated with the partial write operation to a high bandwidth memory communicatively coupled to the plurality of tiles when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state.
16. The non-transitory computer-readable medium of claim 15 , comprising instructions which, when executed by a processor, configure the processor to:
implement a write through cache operation when the cache line is in an exclusive state.
17. The non-transitory computer-readable medium of claim 16 , comprising instructions which, when executed by a processor, configure the processor to:
disable a partial write management protocol in response to detecting a partial write disable state flag.
18. The non-transitory computer-readable medium of claim 17 , wherein the partial write disable state flag is set by a compute state command.
19. The non-transitory computer-readable medium of claim 17 , wherein the partial write disable state flag is set by an application via an input to an application programming interface (API).
20. The computer-implemented method of claim 19 , comprising instructions which, when executed by a processor, configure the processor to:
disable the partial write management protocol for 256 byte blocks of cache in response to the partial write disable flag.
21. The non-transitory computer-readable medium of claim 20 , comprising instructions which, when executed by a processor, configure the processor to:
disable compression operations for the local cache.