Memory configuration for implementing a neural network

1. An apparatus comprising:

circuitry configured to implement a neural network and comprising a plurality of unit cells, wherein a given one of the plurality of unit cells comprises one or more static random-access memory cells and a digital to analog converter device, wherein the one or more static random-access memory cells implement an n-bit static-access memory, wherein the digital to analog converter device is configured to receive one or more outputs produced by respective ones of the one or more static random-access memory cells, and wherein the given unit cell further comprises a set of transistors forming at least one cross-coupled inverter and a set of programming transistors coupling the cross-coupled inverter to a set of bit-lines associated with the given unit cell; and

at least one processor operatively coupled to a memory and configured to:

initialize weights of the neural network by programming the unit cells;

determine an amount of error associated with the initialized weights; and

adjust the initialized weights in response to the amount of error exceeding a threshold amount of error.

2. The apparatus of claim 1 , wherein the digital to analog converter device comprises a resistor ladder.

3. The apparatus of claim 2 , wherein the resistor ladder is an R-2R resistor ladder.

4. The apparatus of claim 2 , wherein the resistor ladder is comprised of a precision resistor material.

5. The apparatus of claim 4 , wherein the precision resistor material comprises polysilicon or a back-end-of-line metal.

6. The apparatus of claim 1 , wherein the digital to analog converter device comprises a field-effect transistor.

7. The apparatus of claim 1 , wherein the n-bit static-access memory is a five bit static-access memory.

8. The apparatus of claim 1 , wherein the given unit cell comprises four transistors forming the at least one cross-coupled inverter and two programming transistors coupling the cross-coupled inverter to the set of bit-lines associated with the given unit cell.

9. The apparatus of claim 1 , wherein the neural network is a feedforward neural network.

10. The apparatus of claim 9 , wherein the neural network is a convolutional neural network.

11. The apparatus of claim 1 , wherein the neural network is a recurring neural network.

12. A method for implementing a neural network, the method comprising:

initializing weights of the neural network by programming a plurality of unit cells, wherein a given one of the plurality of unit cells comprises one or more static random-access memory cells and a digital to analog converter device, wherein the one or more static random-access memory cells implement an n-bit static-access memory, wherein the digital to analog converter device is configured to receive one or more outputs produced by respective ones of the one or more static random-access memory cells, and wherein the given unit cell further comprises a set of transistors forming at least one cross-coupled inverter and a set of programming transistors coupling the cross-coupled inverter to a set of bit-lines associated with the given unit cell;

determining an amount of error associated with the initialized weights; and

adjusting the initialized weights in response to the amount of error exceeding a threshold amount of error;

wherein the steps of the method are implemented by at least one processing device comprising a processor operatively coupled to a memory.

13. The method of claim 12 , wherein the digital to analog converter device comprises a resistor ladder.

14. The method of claim 13 , wherein the resistor ladder is an R-2R resistor ladder.

15. The method of claim 13 , wherein the resistor ladder is comprised of a precision resistor material.

16. The method of claim 12 , wherein the digital to analog converter device comprises a field-effect transistor.

17. The method of claim 12 , wherein the n-bit static-access memory is a five bit static-access memory.

18. The method of claim 12 , wherein the given unit cell comprises four transistors forming the at least one cross-coupled inverter and two programming transistors coupling the cross-coupled inverter to the set of bit-lines associated with the given unit cell.

19. The method of claim 12 , wherein the neural network is one of a feedforward neural network and a recurring neural network.

20. An article of manufacture comprising a processor-readable storage medium for storing computer-readable program code which, when executed, causes at least one processor to implement a neural network by performing steps of:

initializing weights of the neural network by programming a plurality of unit cells, wherein a given one of the plurality of unit cells comprises one or more static random-access memory cells and a digital to analog converter device, wherein the one or more static random-access memory cells implement an n-bit static-access memory, wherein the digital to analog converter device is configured to receive one or more outputs produced by respective ones of the one or more static random-access memory cells, and wherein the given unit cell further comprises a set of transistors forming at least one cross-coupled inverter and a set of programming transistors coupling the cross-coupled inverter to a set of bit-lines associated with the given unit cell;

determining an amount of error associated with the initialized weights; and

adjusting the initialized weights in response to the amount of error exceeding a threshold amount of error.