Gate drive circuit, touch display device and driving method
A gate drive circuit, a touch display device and a driving method are provided. The gate drive circuit includes a plurality of cascaded shift register units and a voltage stabilization circuit. Each of the plurality of cascaded shift register units includes a touch scanning control terminal; and the voltage stabilization circuit is connected to a first shift register unit and at least one second shift register unit after the first shift register unit, of the plurality of cascaded shift register units, and configured to compensate a level of a first node of the group of second shift register units in response to the touch scanning control signal.
1. A gate drive circuit, comprising:
a plurality of cascaded shift register units, wherein each of the plurality of cascaded shift register units comprises a touch scanning control terminal, and the touch scanning control terminal is configured to receive a touch scanning control signal; and
a voltage stabilization circuit, connected to a first shift register unit and a group of second shift register units after the first shift register unit, of the plurality of cascaded shift register units, and configured to compensate a level of a first node of the group of second shift register units in response to the touch scanning control signal,
wherein the group of second shift register units comprises at least one second shift register unit;
each of the plurality of cascaded shift register units further comprises an input terminal which is configured to control the level of the first node of the group of second shift register units according to an input signal,
the voltage stabilization circuit is electrically connected to a first node of the first shift register unit and is electrically connected to an input terminal of the group of second shift register units, and is configured to compensate the level of the first node of the group of second shift register units under control of the touch scanning control signal and a level of the first node of the first shift resister unit;
the voltage stabilization circuit comprises an input sub-circuit, a voltage stabilization switch sub-circuit and an output sub-circuit;
the input sub-circuit is configured to input the touch scanning control signal to the voltage stabilization switch sub-circuit in response to the touch scanning control signal;
the voltage stabilization switch sub-circuit is configured to charge the first node of the first shift register unit; and
the output sub-circuit is configured to output the touch scanning control signal to the input terminal of the group of second shift register units under control of the level of the first node of the first shift register unit.
2. The gate drive circuit according to claim 1 ,
wherein the input sub-circuit comprises a first transistor, a gate electrode of the first transistor is connected to a first electrode of the first transistor and configured to receive the touch scanning control signal, and a second electrode of the first transistor is configured to be connected to the voltage stabilization switch sub-circuit.
3. The gate drive circuit according to claim 2 ,
wherein the voltage stabilization switch sub-circuit comprises a second transistor, a first electrode of the second transistor is configured to be connected to the second electrode of the first transistor, and a gate electrode of the second transistor is connected to a second electrode of the second transistor and is configured to be connected to the first node of the first shift register unit to charge the first node of the first shift register unit.
4. The gate drive circuit according to claim 2 ,
wherein the output sub-circuit comprises a third transistor, a gate electrode of the third transistor is configured to be connected to the first node of the first shift register unit, a first electrode of the third transistor is configured to receive the touch scanning control signal, and a second electrode of the third transistor is configured to be connected to the input terminal of the group of second shift register units.
5. The gate drive circuit according to claim 1 ,
wherein the input sub-circuit comprises a first transistor, a gate electrode of the first transistor is configured to receive the touch scanning control signal, a first electrode of the first transistor is connected to the input terminal of the group of second shift register units, and a second electrode of the first transistor is configured to be connected to the voltage stabilization switch sub-circuit.
6. The gate drive circuit according to claim 1 , wherein each of the plurality of cascaded shift register units further comprises an input terminal, and the voltage stabilization circuit is electrically connected to an input terminal of the group of second shift register units;
the voltage stabilization circuit is configured to output a charging control signal to the input terminal of the group of second shift register units in response to the touch scanning control signal to compensate the level of the first node of the group of second shift register units.
7. The gate drive circuit according to claim 1 , wherein each of the plurality of cascaded shift register units further comprises an output terminal, an input circuit, a first node reset circuit, an output circuit and a touch noise reduction circuit;
an input circuit of an M-th stage of shift register unit in the plurality of cascaded shift register units is configured to charge a first node of the M-th stage of shift register unit in response to an input signal;
a first node reset circuit of the M-th stage of shift register unit is configured to reset the first node of the M-th stage of shift register unit in response to a reset signal;
an output circuit of the M-th stage of shift register unit is configured to output a clock signal to an output terminal of the M-th stage of shift register unit under control of a level of the first node of the M-th stage of shift register unit; and
a touch noise reduction circuit of the M-th stage of shift register unit is configured to reset the output terminal of the M-th stage of shift register unit in response to the touch scanning control signal,
wherein M is a positive integer and is less than or equal to an amount of the plurality of cascaded shift register units.
8. The gate drive circuit according to claim 7 , wherein each of the plurality of cascaded shift register units further comprises a pull-down circuit, a pull-down control circuit, a first node noise reduction circuit, and an output noise reduction circuit;
a pull-down circuit of the M-th stage of shift register unit is configured to control a level of a second node of the M-th stage of shift register unit under control of the level of the first node of the M-th stage of shift register unit and a level of a pull-down control node of the M-th stage of shift register unit;
a pull-down control circuit of the M-th stage of shift register unit is configured to control the level of the pull-down control node of the M-th stage of shift register unit under control of the level of the first node of the M-th stage of shift register unit;
a first node noise reduction circuit of the M-th stage of shift register unit is configured to perform noise reduction on the first node of the M-th stage of shift register unit under control of the level of the second node of the M-th stage of shift register unit; and
an output noise reduction circuit of the M-th stage of shift register unit is configured to perform noise reduction on the output terminal of the M-th stage of shift register unit under control of the level of the second node of the M-th stage of shift register unit.
9. The gate drive circuit according to claim 1 , further comprising a first clock signal line and a second clock signal line,
wherein each of the plurality of cascaded shift register units further comprises a clock signal terminal,
the first clock signal line is connected to a clock signal terminal of a (2N−1)-th stage of shift register unit of the plurality of cascaded shift register units, and the second clock signal line is connected to a clock signal terminal of a 2N-th stage of shift register unit of the plurality of cascaded shift register units; and
N is an integer greater than 0.
10. The gate drive circuit according to claim 9 , wherein each of the plurality of cascaded shift register units further comprises an input terminal, an output terminal and a reset terminal, and the group of second shift register units comprises only one second shift register unit;
an N-th stage of shift register unit of the plurality of cascaded shift register units is the first shift register unit, and a first node of the N-th stage of shift register unit is connected to the voltage stabilization circuit;
an (N+1)-th stage of shift register unit of the plurality of cascaded shift register units is the second shift register unit, and an input terminal of the (N+1)-th stage of shift register unit is connected to the voltage stabilization circuit;
except for a last stage of shift register unit, a reset terminal of an n 1 -th stage of shift register unit of the plurality of cascaded shift register units is connected to an output terminal of an (n 1 +1)-th stage of shift register unit of the plurality of cascaded shift register units;
except for a first stage of shift register unit and the (N+1)-th stage of shift register unit, an input terminal of an n 2 -th stage of shift register unit in the plurality of cascaded shift register units is connected to an output terminal of the (n 2 −1)-th stage of shift register unit in the plurality of cascaded shift register units; and
an amount of the plurality of cascaded shift register units is Q, N, Q, n 1 and n 2 are integers, 1<Q, 1≤N<Q, 0<n 1 <Q, 1<n 2 ≤Q, and n 2 ≠N+1.
11. A driving method for driving the gate drive circuit according to claim 10 , comprising:
in a first phase, controlling an output terminal of the N-th stage of shift register unit to output an N-th gate scanning signal;
in a touch scanning phase, inputting the touch scanning control signal by a touch scanning control signal line, to compensate a level of a first node of the (N+1)-th stage of shift register unit; and
in a second phase, controlling an output terminal of the (N+1)-th stage of shift register unit to output an (N+1)-th gate scanning signal based on the level, which is compensated, of the first node of the (N+1)-th stage of shift register unit.
12. The gate drive circuit according to claim 1 , further comprising a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line,
wherein each of the plurality of cascaded shift register units further comprises a clock signal terminal,
the first clock signal line is connected to a clock signal terminal of a (4n 3 −3)-th stage of shift register unit of the plurality of cascaded shift register units, the second clock signal line is connected to a clock signal terminal of a (4n 3 −2)-th stage of shift register unit of the plurality of cascaded shift register units, the third clock signal line is connected to a clock signal terminal of a (4n 3 −1)-th stage of shift register unit of the plurality of cascaded shift register units, and the fourth clock signal line is connected to a clock signal terminal of a 4n 3 -th stage of shift register unit of the plurality of cascaded shift register units; and
n 3 is an integer greater than 0.
13. The gate drive circuit according to claim 1 , further comprising a touch scanning control signal line,
wherein the touch scanning control terminal of each of the plurality of cascaded shift register units and the voltage stabilization circuit are electrically connected to the touch scanning control signal line to receive the touch scanning control signal.
14. A touch display device, comprising the gate drive circuit according to claim 1 .
15. A driving method for driving the gate drive circuit according to claim 1 , comprising:
in a first phase, controlling the first shift register unit to output a gate scanning signal;
in a touch scanning phase, inputting the touch scanning control signal by a touch scanning control signal line, to compensate the level of the first node of the group of second shift register units; and
in a second phase, controlling the group of second shift register units to output a group of gate scanning signals based on the level, which is compensated, of the first node of the group of second shift register units.
16. The gate drive circuit according to claim 1 , wherein the voltage stabilization circuit is configured to output the touch scanning control signal to the input terminal of the group of second shift register units to compensate the level of the first node of the group of second shift register units under control of the touch scanning control signal and the level of the first node of the first shift register unit.
17. A gate drive circuit, comprising:
a plurality of cascaded shift register units, wherein each of the plurality of cascaded shift register units comprises a touch scanning control terminal, and the touch scanning control terminal is configured to receive a touch scanning control signal; and
a voltage stabilization circuit, connected to a first shift register unit and a group of second shift register units after the first shift register unit, of the plurality of cascaded shift register units, and configured to compensate a level of a first node of the group of second shift register units in response to the touch scanning control signal,
wherein the group of second shift register units comprises at least one second shift register unit;
the gate drive circuit further comprises a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; each of the plurality of cascaded shift register units further comprises a clock signal terminal; the first clock signal line is connected to a clock signal terminal of a (4n 3 −3)-th stage of shift register unit of the plurality of cascaded shift register units, the second clock signal line is connected to a clock signal terminal of a (4n 3 −2)-th stage of shift register unit of the plurality of cascaded shift register units, the third clock signal line is connected to a clock signal terminal of a (4n 3 −1)-th stage of shift register unit of the plurality of cascaded shift register units, and the fourth clock signal line is connected to a clock signal terminal of a 4n 3 -th stage of shift register unit of the plurality of cascaded shift register units; and n 3 is an integer greater than 0;
each of the plurality of cascaded shift register units further comprises an input terminal, an output terminal and a reset terminal, and the group of second shift register units comprises two second shift register units;
an (N−1)-th stage of shift register unit of the plurality of cascaded shift register units is the first shift register unit, and a first node of the (N−1)-th stage of shift register unit is connected to the voltage stabilization circuit;
both an (N+1)-th stage of shift register unit and an (N+2)-th stage of shift register unit of the plurality of cascaded shift register units are the second shift register units, and both an input terminal of the (N+1)-th stage of shift register unit and an input terminal of the (N+2)-th stage of shift register unit are connected to the voltage stabilization circuit;
except for last two stages of shift register units, a reset terminal of an n 4 -th stage of shift register unit of the plurality of cascaded shift register units is connected to an output terminal of an (n 4 −2)-th stage of shift register unit of the plurality of cascaded shift register units;
except for a first stage of shift register unit, a second stage of shift register unit, the (N+1)-th stage of shift register unit and the (N+2)-th stage of shift register unit, an input terminal of an n 5 -th stage of shift register unit of the plurality of cascaded shift register units is connected to an output terminal of the (n 5 +2)-th stage of shift register unit of the plurality of cascaded shift register units; and
an amount of the plurality of cascaded shift register units is Q, N, Q, n 4 and n 5 are integers, 3<Q, 2≤N<Q−1, 0<n 4 <Q−1, 2<n 5 ≤Q, and n 5 ≠N+1, n 5 ≠N+2.
18. A driving method for driving the gate drive circuit according to claim 17 , comprising:
in a first phase, controlling an output terminal of the (N−1)-th stage of shift register unit to output an (N−1)-th gate scanning signal;
in a third phase, controlling an output terminal of an N-th stage of shift register unit of the plurality of cascaded shift register units to output an N-th gate scanning signal;
in a touch scanning phase, inputting the touch scanning control signal by a touch scanning control signal line, to compensate a level of a first node of the (N+1)-th stage of shift register unit and a level of a first node of the (N+2)-th stage of shift register unit; and
in a second phase, controlling an output terminal of the (N+1)-th stage of shift register unit to output an (N+1)-th gate scanning signal based on the level, which is compensated, of the first node of the (N+1)-th stage of shift register unit, and controlling an output terminal of the (N+2)-th stage of shift register unit to output an (N+2)-th gate scanning signal based on the level, which is compensated, of the first node of the (N+2)-th stage of shift register unit.