Three-dimensional semiconductor memory devices

1. A three-dimensional semiconductor memory device comprising:

an electrode structure including a plurality of gate electrodes stacked in a first direction that is perpendicular to a top surface of a substrate;

a lower pattern group including a plurality of lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate; and

an upper pattern group including a plurality of upper vertical patterns that are in an upper portion of the electrode structure,

wherein the plurality of upper vertical patterns are connected to the plurality of lower vertical patterns, respectively,

wherein the upper pattern group comprises an upper sub-group including a group of the plurality of upper vertical patterns arranged in a zigzag fashion along a second direction that is parallel to the top surface of the substrate,

wherein a pair of directly adjacent ones of the plurality of upper vertical patterns in the upper sub-group are spaced apart from each other by a first distance,

wherein the lower pattern group comprises a lower sub-group including a group of the plurality of lower vertical patterns arranged in a zigzag fashion along the second direction, and

wherein a pair of directly adjacent ones of the plurality of lower vertical patterns in the lower sub-group are spaced apart from each other by a second distance that is greater than the first distance.

2. The three-dimensional semiconductor memory device of claim 1 , further comprising two common source plugs spaced apart from each other in the second direction, wherein the electrode structure is between the two common source plugs.

3. The three-dimensional semiconductor memory device of claim 2 , further comprising two common source regions in the substrate and spaced apart from each other in the second direction, wherein the electrode structure is between the two common source regions, and

wherein the two common source plugs are connected to the two common source regions, respectively.

4. The three-dimensional semiconductor memory device of claim 2 , wherein the plurality of lower vertical patterns comprise an outermost lower vertical pattern that is closest to one of the two common source plugs, and the plurality of upper vertical patterns comprise an outermost upper vertical pattern that is closest to the one of the two common source plugs, and

wherein a midpoint of an upper surface of the outermost lower vertical pattern is offset from a midpoint of a lower surface of the outermost upper vertical pattern by a third distance toward the one of the two common source plugs.

5. The three-dimensional semiconductor memory device of claim 4 , wherein the plurality of lower vertical patterns further comprise a second outermost lower vertical pattern that is closest to the outermost lower vertical pattern and is spaced apart from the outermost lower vertical pattern in the second direction, and the plurality of upper vertical patterns further comprises a second outermost upper vertical pattern that is closest to the outermost upper vertical pattern and is spaced apart from the outermost upper vertical pattern in the second direction,

wherein a midpoint of an upper surface of the second outermost lower vertical pattern is offset from a midpoint of a lower surface of the second outermost upper vertical pattern by a fourth distance toward the one of the two common source plugs, and wherein the third distance is greater than the fourth distance.

6. The three-dimensional semiconductor memory device of claim 1 , wherein the electrode structure comprises opposing sides that are spaced apart from each other in the second direction, and

wherein the opposing sides of the electrode structure are sloped relative to the top surface of the substrate, and a width of a top end of the electrode structure is less than a width of a bottom end of the electrode structure.

7. The three-dimensional semiconductor memory device of claim 1 , wherein each of the plurality of lower vertical patterns comprises:

one of a plurality of lower vertical channels, wherein the plurality of lower vertical channels are in the lower portion of the electrode structure and are connected to the substrate; and

one of a plurality of lower conductive pads,

wherein the plurality of lower conductive pads are on the plurality of lower vertical channels, respectively, and

wherein the plurality of upper vertical patterns are connected to the plurality of lower conductive pads, respectively.

8. The three-dimensional semiconductor memory device of claim 7 , wherein each of the plurality of upper vertical patterns comprises:

one of a plurality of upper vertical channels, wherein the plurality of upper vertical channels are in the upper portion of the electrode structure and are connected to the plurality of lower conductive pads, respectively; and

one of a plurality of upper conductive pads, wherein the plurality of upper conductive pads are on the plurality of upper vertical channels, respectively.

9. The three-dimensional semiconductor memory device of claim 8 , further comprising a plurality of bit lines on the electrode structure, wherein the plurality of bit lines are spaced apart from each other, and

wherein the plurality of upper vertical patterns are connected to corresponding ones of the plurality of bit lines through corresponding ones of the plurality of upper conductive pads.

10. The three-dimensional semiconductor memory device of claim 1 , wherein a width of an upper portion of one of the plurality of lower vertical patterns is greater than a width of an upper portion of one of the plurality of upper vertical patterns.

11. A three-dimensional semiconductor memory device comprising:

an electrode structure including a plurality of gate electrodes stacked in a first direction that is perpendicular to a top surface of a substrate;

a lower pattern group including a plurality of lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate; and

an upper pattern group including a plurality of upper vertical patterns that are in an upper portion of the electrode structure,

wherein the plurality of upper vertical patterns are connected to the plurality of lower vertical patterns, respectively, and

wherein an upper portion of each of the plurality of lower vertical patterns has a first width in a second direction that is parallel to the top surface of the substrate, an upper portion of each of the plurality of upper vertical patterns has a second width in the second direction, and the first width is greater than the second width.

12. The three-dimensional semiconductor memory device of claim 11 , wherein the electrode structure comprises opposing sides that are spaced apart from each other in the second direction, and

wherein the opposing sides of the electrode structure are sloped relative to the top surface of the substrate, and a width of a top end of the electrode structure is less than a width of a bottom end of the electrode structure.

13. The three-dimensional semiconductor memory device of claim 11 , wherein each of the plurality of lower vertical patterns comprises:

one of a plurality of lower vertical channels, wherein the plurality of lower vertical channels are in the lower portion of the electrode structure and are connected to the substrate; and

one of a plurality of lower conductive pads, wherein the plurality of lower conductive pads are on the plurality of lower vertical channels, respectively, and

wherein the plurality of upper vertical patterns are connected to the plurality of lower conductive pads, respectively.

14. The three-dimensional semiconductor memory device of claim 13 , wherein each of the plurality of upper vertical patterns comprises:

one of a plurality of upper vertical channels, wherein the plurality of upper vertical channels are in the upper portion of the electrode structure and are connected to the plurality of lower conductive pads, respectively; and

one of a plurality of upper conductive pads, wherein the plurality of upper conductive pads are on the plurality of upper vertical channels, respectively.

15. The three-dimensional semiconductor memory device of claim 14 , further comprising a plurality of bit lines on the electrode structure, wherein the plurality of bit lines are spaced apart from each other, and

wherein the plurality of upper vertical patterns are connected to corresponding ones of the plurality of bit lines through corresponding ones of the plurality of upper conductive pads.

16. The three-dimensional semiconductor memory device of claim 11 , further comprising two common source plugs spaced apart from each other in the second direction, wherein the electrode structure is between the two common source plugs.

17. The three-dimensional semiconductor memory device of claim 16 , further comprising two common source regions in the substrate and spaced apart from each other in the second direction, wherein the electrode structure is between the two common source regions, and

wherein the two common source plugs are connected to the two common source regions, respectively.

18. The three-dimensional semiconductor memory device of claim 11 , wherein the upper pattern group comprises an upper sub-group including a group of the plurality of upper vertical patterns arranged along the second direction,

wherein a pair of directly adjacent ones of the plurality of upper vertical patterns in the upper sub-group are spaced apart from each other by a first distance,

wherein the lower pattern group comprises a lower sub-group including a group of the plurality of lower vertical patterns arranged along the second direction, and

wherein a pair of directly adjacent ones of the plurality of lower vertical patterns in the lower sub-group are spaced apart from each other by a second distance that is greater than the first distance.

19. The three-dimensional semiconductor memory device of claim 11 , wherein the electrode structure comprises opposing sides that are spaced apart from each other in the second direction,

wherein the plurality of lower vertical patterns comprises a first lower vertical pattern, a second lower vertical pattern that is directly adjacent to the first lower vertical pattern, and a third lower vertical pattern directly adjacent to the second lower vertical pattern,

wherein the second lower vertical pattern is between the first lower vertical pattern and the third lower vertical pattern, and the third lower vertical pattern is closest to one of the opposing sides of the electrode structure,

wherein the first lower vertical pattern and the second lower vertical pattern are spaced apart from each other by a third distance, the second lower vertical pattern and the third lower vertical pattern are spaced apart from each other by a fourth distance, and the third distance is less than the fourth distance.

20. The three-dimensional semiconductor memory device of claim 11 , wherein the electrode structure comprises opposing sides that are spaced apart from each other in the second direction,

wherein the plurality of lower vertical patterns comprise an outermost lower vertical pattern that is closest to one of the opposing sides of the electrode structure, and the plurality of upper vertical patterns comprise an outermost upper vertical pattern that is closest to the one of the opposing sides of the electrode structure, and

wherein a midpoint of an upper surface of the outermost lower vertical pattern is offset from a midpoint of a lower surface of the outermost upper vertical pattern toward the one of the opposing sides of the electrode structure.