IP Library › Granted Patent US 11,302,773
Granted Patent B2
US 11,302,773 · App. 16/155,694 · Granted Apr 12, 2022

Back-end-of-line integrated metal-insulator-metal capacitor

Inventors: Ye Lu (San Diego, CA); Junjing Bao (San Diego, CA); Haitao Cheng (San Jose, CA); Chao Song (San Diego, CA)
Assignee: Qualcomm Incorporated
H01L28/60H01L23/5223H01L28/65H01L23/53209H01L23/53228H01L23/53242H01L23/53257
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Quick Facts
Patent No.
US 11,302,773
App. No.
16/155,694
Granted
Apr 12, 2022
Kind
B2
Abstract

A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.

Claims (41)

1. A capacitor, comprising:

a first electrode comprising a conductive back-end-of-line layer;

a second electrode comprising a nitride based metal;

an etch stop layer between the first electrode and the second electrode;

a conductive plate above the etch stop layer; and

a dielectric between the conductive plate and the etch stop layer,

wherein each of the first and the second electrodes includes a via connecting to upper layer routing, and

wherein the upper layer routing includes corresponding power-supply rails for the first and second electrodes.

2. The capacitor of claim 1 , in which the etch stop layer comprises a high-K material or a combination of the high-K material and a low-K material.

3. The capacitor of claim 1 , in which the etch stop layer comprises a combination of oxygen doped carbon and aluminum nitride.

4. The capacitor of claim 3 , in which the etch stop layer further comprises oxygen doped aluminum.

5. The capacitor of claim 1 , in which the etch stop layer is in one layer of a lower four back-end-of-line layers.

6. The capacitor of claim 1 , in which the etch stop layer comprises a thickness between five to ten nanometers.

7. The capacitor of claim 1 , in which the first electrode comprises copper (Cu), cobalt (Co), or ruthenium (Ru).

8. The capacitor of claim 1 , in which the second electrode comprises titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN).

9. A method of fabricating a capacitor, comprising:

forming a first electrode comprising a conductive back-end-of-line (BEOL) layer;

depositing an etch stop layer on the first electrode;

fabricating a second electrode, including a nitride based metal, on the etch stop layer;

forming a conductive plate above the etch stop layer;

forming a dielectric between the conductive plate and the etch stop layer; and

forming each of the first and the second electrodes to upper layer routing,

wherein the upper layer routing includes corresponding power-supply rails for the first and second electrodes.

10. The method of claim 9 , in which depositing the etch stop layer comprises depositing a high-K material or a combination of the high-K material and a low-K material.

11. The method of claim 9 , in which depositing the etch stop layer comprises depositing a combination of oxygen doped carbon and aluminum nitride.

12. The method of claim 9 , in which depositing the etch stop layer further comprises depositing oxygen doped aluminum.

13. The method of claim 9 , further comprising depositing the etch stop layer in one layer of a lower four back-end-of-line layers.

14. The method of claim 9 , in which depositing the etch stop layer comprises depositing the etch stop layer with a thickness between five to ten nanometers.

15. A capacitor, comprising:

means for interconnecting fabricated devices and wiring interconnects on a substrate;

an electrode comprising a nitride based metal;

an etch stop layer between the interconnecting means and the electrode;

a conductive plate above the etch stop layer; and

a dielectric between the conductive plate and the etch stop layer,

wherein the electrode includes a via connecting to upper layer routing, and

wherein the upper layer routing includes a power-supply rail for the electrode.

16. The capacitor of claim 15 , in which the etch stop layer comprises a high-K material or a combination of the high-K material and a low-K material.

17. The capacitor of claim 15 , in which the etch stop layer comprises a combination of oxygen doped carbon and aluminum nitride.

18. The capacitor of claim 17 , in which the etch stop layer further comprises oxygen doped aluminum.

19. The capacitor of claim 15 , in which the etch stop layer is in one layer of a lower four back-end-of-line layers.

20. The capacitor of claim 15 , in which the etch stop layer comprises a thickness between five to ten nanometers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2019
From: LU, YE; BAO, JUNJING; CHENG, HAITAO; SONG, CHAO
To: QUALCOMM INCORPORATED
Reel/Frame 047946/0632 →
Continuity (1)
Related Publication 20200111865A1 · Apr 9, 2020