Integrated circuit layouts with source and drain contacts of different widths

1. A semiconductor device comprising:

an active region in a substrate, wherein the active region extends in a first direction;

a gate structure extending in a second direction different from the first direction, wherein the gate structure extends across the active region; and

a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure, wherein a first source/drain contact of the plurality of source/drain contacts has a first width, a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width, and a spacing between the first source/drain contact and the gate structure is smaller than a spacing between the second source/drain contact and the gate structure.

2. The semiconductor device of claim 1 , further comprising a conductive layer extending in the first direction, wherein the conductive layer is electrically coupled to the first source/drain contact and the second source/drain contact.

3. The semiconductor device of claim 2 , further comprising a first via, wherein the first via electrically couples the conductive layer to the first source/drain contact.

4. The semiconductor device of claim 3 , further comprising a second via, wherein the second via electrically couples the conductive layer to the second source/drain contact.

5. The semiconductor device of claim 4 , wherein the first via has a dimension greater than a dimension of the second via.

6. The semiconductor device of claim 1 , wherein the second width is constant in a third direction perpendicular to both the first direction and the second direction.

7. A semiconductor device comprising:

a plurality of active regions in a substrate, wherein each of the plurality of active regions extends in a first direction and is separated from one another in a second direction different from the first direction;

a plurality of gate structures extending in the second direction, wherein each of the plurality of gate structures extends across each active region of the plurality of active regions;

a plurality of first source/drain contacts extending in the second direction and overlapping a plurality of first source/drain regions in a first active region of the plurality of active regions on opposite sides of the plurality of gate structures, wherein a first set of first source/drain contacts of the plurality of first source/drain contacts have a first width, a second set of first source/drain contacts of the plurality of first source/drain contacts have a second width, the first width and the second width are constant in a direction perpendicular to a top surface of the substrate, and the second width less than the first width;

a plurality of second source/drain contacts extending in the second direction and overlapping a plurality of second source/drain regions in a second active region of the plurality of active regions on opposite sides of the plurality of gate structures, wherein a first set of second source/drain contacts of the plurality of second source/drain contacts have the first width, and a second set of second source/drain contacts of the plurality of second source/drain contacts have the second width; and

a plurality of interconnect structures extending in the second direction, wherein each interconnect structure of the plurality of interconnect structures is electrically coupled to a corresponding first source/drain contact of the plurality of first source/drain contacts and a corresponding second source/drain contact of the plurality of second source/drain contacts.

8. The semiconductor device of claim 7 , further comprising one or more isolation structures separating the plurality of active regions from one another.

9. The semiconductor device of claim 7 , wherein at least one interconnect structure of the plurality of interconnect structures is in direct contact with the corresponding first source/drain contact of the plurality of first source/drain contacts and the corresponding second source/drain contact of the plurality of second source/drain contacts.

10. The semiconductor device of claim 7 , further comprising a plurality of first vias coupling the plurality of interconnect structures to corresponding first source/drain contacts of the plurality of first source/drain contacts and a plurality of second vias coupling the plurality of interconnect structures to corresponding second source/drain contacts of the plurality of second source/drain contacts.

11. The semiconductor device of claim 10 , wherein each interconnect structure of the plurality of interconnect structures is coupled to the corresponding first source/drain contact of the plurality of first source/drain contacts through a corresponding first via of the plurality of first vias, and to the corresponding second source/drain contact of the plurality of second source/drain contacts through a corresponding second via of the plurality of second vias.

12. The semiconductor device of claim 10 , wherein a first set of first vias of the plurality of first vias contacting the first set of first source/drain contacts of the plurality of first source/drain contacts have a dimension greater than a dimension of a second set of first vias of the plurality of first vias contacting the second set of first source/drain contacts of the plurality of first source/drain contacts.

13. The semiconductor device of claim 10 , wherein a first set of second vias of the plurality of second vias contacting the first set of second source/drain contacts of the plurality of second source/drain contacts have a dimension greater than a dimension of a second set of second vias of the plurality of second vias contacting the second set of second source/drain contacts of the plurality of second source/drain contacts.

14. The semiconductor device of claim 7 , wherein adjacent gate structures of the plurality of gate structures have a uniform pitch.

15. The semiconductor device of claim 7 , wherein the plurality of first source/drain regions comprises dopants of a first conductivity type, and the plurality of second source/drain regions comprises dopants of a second conductivity type.

16. The semiconductor device of claim 15 , wherein the first conductivity is the same as the second conductivity type.

17. The semiconductor device of claim 15 , wherein the first conductivity is different from the second conductivity type.

18. A semiconductor device comprising:

an active region in a substrate, wherein the active region extends in a first direction;

a gate structure extending in a second direction different from the first direction, wherein the gate structure overlaps the active region;

a conductive layer extending in the first direction, wherein the conductive layer overlaps a portion of the gate structure;

a first source/drain (S/D) contact extending in the second direction, wherein the first S/D contact overlaps the active region on a first side of the gate structure, and an upper-most portion of the first S/D contact is a first distance from the gate structure;

a second S/D contact extending in the second direction, wherein the second S/D contact overlaps the active region on a second side of the gate structure opposite the first side, an upper-most portion of the second S/D contact is a second distance from the gate structure, and the second distance is different from the first distance;

a first via electrically connecting the conductive layer to the first S/D contact, wherein the first via has a first width in the first direction; and

a second via electrically connecting the conductive layer to the second S/D contact, wherein the second via has a second width in the first direction, and the second width is less than the first width.

19. The semiconductor device of claim 18 , wherein the first S/D contact has a third width in the first direction, the second S/D contact has a fourth width in the first direction, and the third width is greater than the fourth width.

20. The semiconductor device of claim 19 , wherein the third width is equal to the first width.