Self-aligned spacers for multi-gate devices and method of fabrication thereof
A semiconductor device includes a substrate; a channel member above the substrate; a gate structure wrapping the channel member; a source/drain (S/D) feature abutting the channel member; and an inner spacer interposing the S/D feature and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the channel member.
1. A semiconductor device, comprising:
a substrate;
a channel member above the substrate;
a gate structure wrapping the channel member;
a source/drain (S/D) feature abutting the channel member; and
an inner spacer interposing the S/D feature and the gate structure, wherein a first sidewall of the inner spacer facing the gate structure has a curvature surface in a cross-sectional view perpendicular to a top surface of the substrate and along a lengthwise direction of the channel member, and wherein a middle portion of the curvature surface bends towards the S/D feature and away from the gate structure.
2. The semiconductor device of claim 1 , wherein the concave surface has a depth in a range from about 0.5 nm to about 5 nm measured along the lengthwise direction of the channel member.
3. The semiconductor device of claim 1 , wherein a second sidewall of the inner spacer facing the S/D feature is substantially perpendicular to the top surface of the substrate.
4. The semiconductor device of claim 1 , wherein the first sidewall of the inner spacer has a convex surface extending outwardly towards the gate structure in a cross-sectional view parallel to the top surface of the substrate and along the lengthwise direction of the channel member.
5. The semiconductor device of claim 4 , wherein the convex surface includes two curvature segments intersecting at an apex.
6. The semiconductor device of claim 5 , wherein each of the two curvature segments bends inwardly away from the gate structure.
7. The semiconductor device of claim 1 , wherein the channel member is a nanosheet.
8. The semiconductor device of claim 1 , wherein the inner spacer includes a dielectric material selected from the group of SiN, SiOC, SiCN, and SiO 2 .
9. The semiconductor device of claim 1 , further comprising:
a gate spacer over sidewalls of the gate structure, wherein the gate structure extends directly under the gate spacer.
10. The semiconductor device of claim 1 , wherein the inner spacer extends directly under the S/D feature.
11. A semiconductor device, comprising:
a substrate;
a plurality of nanosheets vertically stacked over each other and above the substrate;
a gate structure disposed over a channel region of the plurality of nanosheets and surrounding each of the nanosheets;
an epitaxial source/drain (S/D) feature adjacent the plurality of nanosheets; and
a dielectric layer sandwiched between the epitaxial S/D feature and the gate structure and surrounding each of the nanosheets,
wherein between two adjacent nanosheets the gate structure has a sidewall bending inwardly away from the dielectric layer from a top view, wherein between the two adjacent nanosheets the dielectric layer has a concave surface interfacing with the gate structure, and wherein the concave surface results in a middle portion of the dielectric layer between the two adjacent nanosheets being thinner than other portions of the dielectric layer that interface with the two adjacent nanosheets.
12. The semiconductor device of claim 11 , wherein the dielectric layer extends directly under the epitaxial S/D feature.
13. The semiconductor device of claim 12 , wherein the dielectric layer separates the epitaxial S/D feature from the substrate.
14. The semiconductor device of claim 11 , wherein a portion of the dielectric layer under a bottommost nanosheet is recessed towards the epitaxial S/D feature more than other portions of the dielectric layer above the bottommost nano sheet.
15. The semiconductor device of claim 11 , further comprising:
a gate spacer over sidewalls of the gate structure, wherein between two adjacent nanosheets the dielectric layer has a thickness substantially the same with the gate spacer.
16. A multi-gate semiconductor device, comprising:
a fin element extending upwardly from a substrate;
a gate structure engaging the fin element;
an epitaxial source/drain (S/D) feature in physical contact with the fin element; and
a dielectric spacer interposing the gate structure and the epitaxial S/D feature, wherein a sidewall surface of the dielectric spacer facing the gate structure has a convex shape in a plane parallel to a top surface of the substrate, the convex shape having an apex extending towards the gate structure.
17. The multi-gate semiconductor device of claim 16 , further comprising:
a gate spacer covering sidewalls of the gate structure, wherein the dielectric spacer has a thickness substantially equal to that of the gate spacer.
18. The multi-gate semiconductor device of claim 17 , wherein a portion of the gate structure extends directly under the gate spacer.
19. The semiconductor device of claim 1 , further comprising:
a gate spacer over sidewalls of the gate structure, wherein a portion of the gate structure interfacing with the curvature surface extends directly under the gate spacer.
20. The semiconductor device of claim 16 , wherein another sidewall surface of the dielectric spacer facing the epitaxial S/D feature is substantially perpendicular to the top surface of the substrate.