Method of making resistive structure of RRAM
View Patent ↗A method for making an RRAM resistive structure includes, step 1, forming a via structure, which includes depositing an ultra-low dielectric constant material layer on a substrate, depositing a copper layer on the ultra-low dielectric constant material layer, depositing a carbon-containing silicon nitride layer, and patterning a via in the carbon-containing silicon nitride layer. step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the via structure without dishing; step 3, forming a first TiN layer on the TaN-filled via structure; and step 4, forming an RRAM resistive structure stack having layers of TaOx, Ta 2 O 5 , Ta, and a second TiN from bottom to top on the first TiN layer, and step 5, patterning the RRAM resistive structure stack the first TiN layer over the TaN-filled via structure to form the RRAM resistive structure.
1. A method for making a Resistive Random-Access Memory (RRAM) resistive structure, comprising:
Step 1, forming a via structure of the RRAM resistive structure;
Step 2, filling the via structure with a TaN layer, followed by planarizing a surface of the TaN layer over the via structure;
Step 3, forming a first TiN layer on the TaN-filled via structure; and
Step 4, patterning an RRAM resistive structure stack on the first TiN layer,
wherein the patterning of the RRAM resistive structure stack stops at a top surface of the first TiN layer.
2. The method for making the RRAM resistive structure, according to claim 1 , wherein forming the via structure in Step 1 comprises depositing a low dielectric constant material layer on a substrate, depositing a copper layer on the low dielectric constant material layer, depositing a carbon-containing silicon nitride layer, and patterning a via in the carbon-containing silicon nitride layer, wherein a bottom of the via exposes the copper layer.
3. The method for making the RRAM resistive structure, according to claim 1 , wherein filling the via structure with the TaN layer in Step 2 applies a deposition method.
4. The method for making the RRAM resistive structure, according to claim 3 , wherein the deposition method in Step 2 is a physical vapor deposition (PVD) process.
5. The method for making the RRAM resistive structure, according to claim 4 , wherein the physical vapor deposition process in Step 2 is a PVD sputtering plate process.
6. The method for making the RRAM resistive structure, according to claim 2 , wherein planarizing the surface of the TaN layer over the via structure in Step 2 comprises terminating the planarization after an upper surface of the carbon-containing silicon nitride layer outside the via is exposed.
7. The method for making the RRAM resistive structure, according to claim 1 , wherein forming the first TiN layer on the via structure in Step 3, comprise a deposition method.
8. The method for making the RRAM resistive structure, according to claim 7 , wherein the deposition method for the first TiN layer is a physical vapor deposition method.
9. The method for making the RRAM resistive structure, according to claim 1 , wherein the RRAM resistive structure stack formed on the first TiN layer in Step 4 comprises at least: a TaOx layer, a Ta 2 O 5 layer, a Ta layer, and a second TiN layer from bottom to top.
10. The method for making the RRAM resistive structure according to claim 9 , wherein x in the TaOx is a fraction that is less than ⅖.
11. The method for making the RRAM resistive structure according to claim 9 , wherein the RRAM resistive structure stack further comprises one or more material layers between the TaOx layer and the Ta 2 O 5 layer, such that no direct contact is between the TaOx layer and the Ta 2 O 5 layer.