Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality
Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.
1. A processor comprising:
decode circuitry to decode an instruction, the instruction having a first field to specify a first source vector register, and a second field to specify a second source vector register, the first source vector register having a plurality of segments, each segment corresponding to one of a plurality of 128-bit lanes and each segment to store a corresponding one of a plurality of 128-bit data blocks of a first source vector, the second source vector register having a plurality segments, each segment corresponding to one of the plurality of 128-bit lanes and each segment to store a corresponding one of a plurality of sets of four 32-bit round keys of a second source vector, each 128-bit data block of the first source vector corresponding to a set of four 32-bit round keys of the second source vector in a same 128-bit lane; and
execution circuitry coupled to the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, to:
encrypt each 128-bit data block of the first source vector by four rounds according to an SM4 cryptographic algorithm using the corresponding set of four 32-bit round keys of the second source vector; and
store the 128-bit data blocks encrypted by the four rounds in the plurality of 128-bit lanes of the first source vector register.
2. The processor of claim 1 , wherein a first set of four 32-bit round keys of the second source vector includes in order round keys RKi, RKi+1, RKi+2, and RKi+3, where i represents a round.
3. The processor of claim 1 , wherein the first source vector comprises 256-bits.
4. The processor of claim 1 , wherein the first source vector comprises 512-bits.
5. The processor of claim 1 , wherein the instruction is an SM4 encryption instruction.
6. The processor of claim 1 , wherein the decode circuitry is able to decode a second, different four round SM4 encryption instruction.
7. The processor of claim 1 , wherein the instruction is an SM4 encryption instruction, and wherein the decode circuitry is able to decode a plurality of additional different SM4 instructions with different opcodes.
8. The processor of claim 1 , wherein the processor is a reduced instruction set computing (RISC) processor.
9. A system on a chip (SoC) comprising:
a memory controller; and
a processor coupled with the memory controller, the processor comprising:
decode circuitry to decode an instruction, the instruction having a first field to specify a first source vector register, and a second field to specify a second source vector register, the first source vector register having a plurality of segments, each segment corresponding to one of a plurality of 128-bit lanes and each segment to store a corresponding one of a plurality of 128-bit data blocks of a first source vector, the second source vector register having a plurality segments, each segment corresponding to one of the plurality of 128-bit lanes and each segment to store a corresponding one of a plurality of sets of four 32-bit round keys of a second source vector, each 128-bit data block of the first source vector corresponding to a set of four 32-bit round keys of the second source vector in a same 128-bit lane; and
execution circuitry coupled to the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, to:
encrypt each 128-bit data block of the first source vector by four rounds according to an SM4 cryptographic algorithm using the corresponding set of four 32-bit round keys of the second source vector; and
store the 128-bit data blocks encrypted by the four rounds in the plurality of 128-bit lanes of the first source vector register.
10. The SoC of claim 9 , wherein a first set of four 32-bit round keys of the second source vector includes in order round keys RKi, RKi+1, RKi+2, and RKi+3, where i represents a round, and further comprising graphics logic coupled with the processor.
11. The SoC of claim 9 , wherein the first source vector comprises 512-bits, and further comprising an image processor coupled with the processor.
12. The SoC of claim 9 , wherein the instruction is an SM4 encryption instruction, and further comprising an audio processor coupled with the processor.
13. The SoC of claim 9 , wherein the decode circuitry is able to decode a second, different four round SM4 encryption instruction, and further comprising a display unit coupled with the processor.
14. The SoC of claim 9 , wherein the instruction is an SM4 encryption instruction, and wherein the decode circuitry is able to decode a plurality of additional different SM4 instructions with different opcodes, and further comprising a media processor coupled with the processor.
15. The SoC of claim 9 , wherein the processor is a reduced instruction set computing (RISC) processor, and further comprising graphics logic coupled with the processor.
16. A system comprising:
a system memory; and
a processor coupled with the system memory, the processor comprising:
decode circuitry to decode an instruction, the instruction having a first field to specify a first source vector register, and a second field to specify a second source vector register, the first source vector register having a plurality of segments, each segment corresponding to one of a plurality of 128-bit lanes and each segment to store a corresponding one of a plurality of 128-bit data blocks of a first source vector, the second source vector register having a plurality segments, each segment corresponding to one of the plurality of 128-bit lanes and each segment to store a corresponding one of a plurality of sets of four 32-bit round keys of a second source vector, each 128-bit data block of the first source vector corresponding to a set of four 32-bit round keys of the second source vector in a same 128-bit lane; and
execution circuitry coupled to the decode circuitry, the execution circuitry to perform operations corresponding to the instruction, to:
encrypt each 128-bit data block of the first source vector by four rounds according to an SM4 cryptographic algorithm using the corresponding set of four 32-bit round keys of the second source vector; and
store the 128-bit data blocks encrypted by the four rounds in the plurality of 128-bit lanes of the first source vector register.
17. The system of claim 16 , wherein a first set of four 32-bit round keys of the second source vector includes in order round keys RKi, RKi+1, RKi+2, and RKi+3, where i represents a round, and further comprising a network controller coupled with the processor.
18. The system of claim 16 , wherein the first source vector comprises 512-bits, and further comprising a communication device coupled with the processor.
19. The system of claim 16 , wherein the instruction is an SM4 encryption instruction, and further comprising a wireless transceiver coupled with the processor.
20. The system of claim 16 , wherein the decode circuitry is able to decode a second, different four round SM4 encryption instruction, and further comprising an I/O device coupled with the processor.
21. The system of claim 16 , wherein the instruction is an SM4 encryption instruction, and wherein the decode circuitry is able to decode a plurality of additional different SM4 instructions with different opcodes, and further comprising a network controller coupled with the processor.
22. The system of claim 16 , wherein the processor is a reduced instruction set computing (RISC) processor, and further comprising a mass storage device coupled with the processor.
23. A method comprising:
decoding an instruction, the instruction having a first field specifying a first source vector register, and a second field specifying a second source vector register, the first source vector register having a plurality of segments, each segment corresponding to one of a plurality of 128-bit lanes and each segment storing a corresponding one of a plurality of 128-bit data blocks of a first source vector, the second source vector register having a plurality segments, each segment corresponding to one of the plurality of 128-bit lanes and each segment storing a corresponding one of a plurality of sets of four 32-bit round keys of a second source vector, each 128-bit data block of the first source vector corresponding to a set of four 32-bit round keys of the second source vector in a same 128-bit lane; and
perform operations corresponding to the instruction, including:
encrypting each 128-bit data block of the first source vector by four rounds according to an SM4 cryptographic algorithm using the corresponding set of four 32-bit round keys of the second source vector; and
storing the 128-bit data blocks encrypted by the four rounds in the plurality of 128-bit lanes of the first source vector register.
24. The method of claim 23 , further comprising:
accessing the first source vector which comprises 512-bits; and
accessing a first set of four 32-bit round keys of the second source vector that include in order round keys RKi, RKi+1, RKi+2, and RKi+3, where i represents a round.
25. The method of claim 23 , wherein the instruction is an SM4 encryption instruction, and further comprising decoding a second, different four round SM4 encryption instruction.
26. The method of claim 23 , wherein the instruction is an SM4 encryption instruction, and further comprising decoding a plurality of additional different SM4 instructions with different opcodes.