IP Library › Granted Patent US 11,303,578
Granted Patent B2
US 11,303,578 · App. 16/884,180 · Granted Apr 12, 2022

Packet processing device and network system

Inventors: Ryohei Yaginiwa (Fuchu, JP); Jumpei Hongo (Kawasaki, JP)
Assignee: FUJITSU LIMITED
H04L47/6275H04L1/1887H04L47/2441H04L49/9094
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Quick Facts
Patent No.
US 11,303,578
App. No.
16/884,180
Granted
Apr 12, 2022
Kind
B2
Abstract

A packet processing device is implemented in a network that transmits priority packets and non-priority packets having a lower priority than the priority packets. The packet processing device includes: a packet storage, a gate, a controller, a detector, a generator, and a transmitter. The packet storage stores non-priority packets. The gate is provided on an output side of the packet storage. The controller controls the gate. The detector detects a transmission pattern of the priority packets. The generator generates, based on the transmission pattern of the priority packets, a gate control signal for controlling a gate of a packet processing device implemented in another node. The transmitter transmits the gate control signal to a destination of the priority packets.

Claims (41)

1. A network system that transmits priority packets and non-priority packets having a lower priority than the priority packets, wherein

a packet processing device is implemented in each node of the network system,

the packet processing device includes

a packet storage that stores non-priority packets,

a gate that is provided on an output side of the packet storage, and

a controller that controls the gate,

an edge node packet processing device is implemented in an edge node of the network system,

the edge node packet processing device further includes

a processor that detects a transmission pattern of the priority packets and generates a gate control signal based on the transmission pattern of the priority packets, and

a transmitter that transmits the gate control signal to a destination of the priority packets,

in the packet processing device that receives the gate control signal, the controller controls the gate according to the gate control signal, and

the transmitter of the edge node packet processing device transmits the gate control signal at an end of a period in which the gate is closed and each packet processing device that receives the gate control signal forwards the gate control signal at an end of a period in which the gate is closed.

2. The network system according to claim 1 , wherein

the transmission pattern indicates intervals at which priority packets arrive at the edge node and a packet amount of priority packets that have arrived at the edge node.

3. The network system according to claim 1 , wherein

the gate control signal indicates a timing for starting to close a gate of another packet processing device and a period of closing the gate of the other packet processing device.

4. A network system that transmits priority packets and non-priority packets having a lower priority than the priority packets, wherein

a packet processing device is implemented in each node of the network system,

the packet processing device includes

a packet storage that stores non-priority packets,

a gate that is provided on an output side of the packet storage, and

a controller that controls the gate,

an edge-node packet processing device is implemented in an edge node of the network system,

the edge-node packet processing device further includes

a processor that detects a transmission pattern of the priority packets and generates a gate control signal based on the transmission pattern of the priority packets, and

a transmitter that transmits the gate control signal to a destination of the priority packets,

in the packet processing device that receives the gate control signal, the controller controls the gate according to the gate control signal, and wherein

the edge-node packet processing device further includes a first port, a second port, and a third port,

a first packet processor and a second packet processor are respectively provided for the first port and the second port in the edge-node packet processing device,

each of the first packet processor and the second packet processor includes the packet storage, the gate, the controller, the processor, and the transmitter,

when the edge-node packet processing device outputs, via the first port, priority packets that have arrived at the third port, information indicating the transmission pattern of the priority packets that has been obtained by the processor of the first packet processor is stored in a memory provided for the first packet processor, and

when the edge-node packet processing device switches a port for outputting priority packets that have arrived at the third port from the first port to the second port, the second packet processor is configured such that

the controller controls the gate by using the information stored in the memory, and

the processor generates the gate control signal by using the information stored in the memory.

5. A packet processing device implemented in a network that transmits priority packets and non-priority packets having a lower priority than the priority packets, the packet processing device comprising:

a packet storage that stores non-priority packets;

a gate that is provided on an output side of the packet storage;

a controller that controls the gate;

a processor that detects a transmission pattern of the priority packets and generates, based on the transmission pattern of the priority packets, a gate control signal for controlling a gate of a packet processing device implemented in another node; and

a transmitter that transmits the gate control signal to a destination of the priority packets, wherein

the transmitter transmits the gate control signal at an end of a period in which the gate is closed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2020
From: YAGINIWA, RYOHEI; HONGO, JUMPEI
To: FUJITSU LIMITED
Reel/Frame 052796/0528 →
Priority Claims (1)
JP JP2019-103519 · Jun 3, 2019 · national
Continuity (1)
Related Publication 20200382436A1 · Dec 3, 2020