IP Library › Granted Patent US 11,304,309
Granted Patent B2
US 11,304,309 · App. 17/048,806 · Granted Apr 12, 2022

Printed circuit board and method for manufacturing printed circuit board

Inventors: Shoichiro Sakai (Osaka, JP); Eiko Imazaki (Osaka, JP); Koji Nitta (Osaka, JP)
Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
H05K3/38C25D3/38C25D5/02C25D5/34C25D21/12H05K1/09H05K3/181
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Quick Facts
Patent No.
US 11,304,309
App. No.
17/048,806
Granted
Apr 12, 2022
Kind
B2
Abstract

A printed circuit board according to an embodiment of the present disclosure includes a base film having an insulating property, and a conductive pattern that is stacked on at least one surface of the base film and that includes a plurality of wiring parts arranged in parallel. The plurality of wiring parts have an average width of 5 μm or more and 15 μm or less. The plurality of wiring parts have an electroless plating layer and an electroplating layer stacked on the electroless plating layer. A void density at an interface between the electroless plating layer and the electroplating layer in a section of the plurality of wiring parts in a thickness direction is 0.01 μm 2 /μm or less.

Claims (22)

1. A printed circuit board comprising:

a base film having an insulating property; and

a conductive pattern that is stacked on at least one surface of the base film and that includes a plurality of wiring parts arranged in parallel,

wherein the plurality of wiring parts have an average width of 5 μm or more and 15 μm or less,

the plurality of wiring parts have an electroless plating layer and an electroplating layer stacked on the electroless plating layer, and

a void density at an interface between the electroless plating layer and the electroplating layer in a section of the plurality of wiring parts in a thickness direction is 0.01 μm 2 /μm or less.

2. The printed circuit board according to claim 1 , wherein a maximum area of a void formed at the interface is 0.01 μm 2 or less.

3. The printed circuit board according to claim 1 , wherein an average spacing of the plurality of wiring parts is 5 μm or more and 15 μm or less.

4. The printed circuit board according to claim 1 , wherein the electroless plating layer and the electroplating layer contain copper as a main component.

5. A method for manufacturing a printed circuit board, comprising a step of forming, by a semi-additive method, a conductive pattern including a plurality of wiring parts arranged in parallel on at least one surface of a base film having an insulating property,

wherein the step of forming includes

an electroless plating step of subjecting the one surface of the base film to electroless plating,

a resist pattern-forming step of forming a resist pattern having an inverted shape of the plurality of wiring parts on a surface of an electroless plating layer formed in the electroless plating step,

a plasma treatment step of subjecting surfaces of the resist pattern and the electroless plating layer after the resist pattern-forming step to plasma treatment, and

an electroplating step of subjecting the surface of the electroless plating layer after the plasma treatment step to electroplating,

the plurality of wiring parts have an average width of 5 μm or more and 15 μm or less, and

an amount of ashing of the resist pattern through the plasma treatment step is 60 nm or more and 300 nm or less.

6. The method for manufacturing a printed circuit board according to claim 5 , wherein an initial current density in the electroplating step is 0.003 A/m 2 or more and 0.015 A/m 2 or less.

7. The printed circuit board according to claim 1 , wherein the void density is 0.001 μm 2 /μm or more and 0.01 μm 2 /μm or less.

8. The printed circuit board according to claim 1 , wherein a void is formed at the interface.

9. The printed circuit board according to claim 8 , wherein a maximum area of the void formed at the interface is 0.01 μm 2 or less.

10. The printed circuit board according to claim 8 , wherein a maximum area of the void formed at the interface is 0.001 μm 2 or more and 0.01 μm 2 or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2020
From: SAKAI, SHOICHIRO; IMAZAKI, EIKO; NITTA, KOJI
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 054197/0547 →
Priority Claims (1)
JP JP2018-092173 · May 11, 2018 · national
Continuity (1)
Related Publication 20210153358A1 · May 20, 2021