Protection liner on interconnect wire to enlarge processing window for overlying interconnect via

1. An integrated chip comprising:

a lower interconnect dielectric layer arranged over a substrate;

an interconnect wire arranged over the lower interconnect dielectric layer;

a first interconnect dielectric layer arranged around outer sidewalls of the interconnect wire;

a protection liner arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire;

a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer;

a second etch stop layer arranged directly on upper surfaces of the protection liner and the first etch stop layer;

a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire; and

an interconnect via extending through the second interconnect dielectric layer, arranged directly over the protection liner, and electrically coupled to the interconnect wire,

wherein the protection liner comprises graphene.

2. The integrated chip of claim 1 , wherein the first etch stop layer is not arranged directly on or over the upper surfaces of the protection liner.

3. The integrated chip of claim 1 , wherein the interconnect via directly contacts the protection liner, the first etch stop layer, and the second etch stop layer.

4. The integrated chip of claim 1 , wherein the interconnect via directly contacts the protection liner.

5. The integrated chip of claim 1 , wherein the protection liner completely covers the outer sidewalls and the top surface of the interconnect wire.

6. The integrated chip of claim 1 , further comprising:

air spacer structures embedded within the first interconnect dielectric layer,

wherein the interconnect wire is laterally between the air spacer structures, and

wherein the first interconnect dielectric layer and the first etch stop layer are vertically between one of the air spacer structures and the interconnect via.

7. The integrated chip of claim 1 , further comprising:

a first barrier layer arranged around the interconnect via and separating the interconnect via from the second interconnect dielectric layer.

8. The integrated chip of claim 7 , wherein the first barrier layer is arranged directly between the interconnect via and the protection liner.

9. An integrated chip comprising:

an interconnect wire arranged over a substrate;

a first interconnect dielectric layer laterally surrounding the interconnect wire;

a protection liner arranged on an upper surface of the interconnect wire and separating the interconnect wire from the first interconnect dielectric layer;

a first etch stop layer arranged over and directly contacting the first interconnect dielectric layer;

a second etch stop layer arranged over and directly contacting the protection liner and the first etch stop layer;

a second interconnect dielectric layer arranged over the second etch stop layer; and

an interconnect via extending through the second interconnect dielectric layer and the second etch stop layer to electrically contact the interconnect wire.

10. The integrated chip of claim 9 , wherein the protection liner is arranged directly between the interconnect via and the interconnect wire.

11. The integrated chip of claim 9 , wherein the protection liner comprises a two-dimensional material.

12. The integrated chip of claim 9 , wherein air spacer structures are embedded within the first interconnect dielectric layer.

13. The integrated chip of claim 9 , wherein the interconnect via has a bottommost surface that is at a first height above the substrate, wherein the first interconnect dielectric layer has a topmost surface that is at a second height above the substrate, and wherein the first height is greater than or equal to the second height.

14. The integrated chip of claim 9 , wherein a portion of the interconnect via directly overlies the first etch stop layer.

15. The integrated chip of claim 9 , wherein the first etch stop layer comprises a different material than the second etch stop layer.

16. A method comprising:

forming a conductive layer over a substrate;

removing portions of the conductive layer to form an interconnect wire over the substrate;

forming a protection liner on outer surfaces of the interconnect wire;

forming a first interconnect dielectric layer around the interconnect wire;

forming a first etch stop layer selectively on the first interconnect dielectric layer and not on the protection liner;

forming a second interconnect dielectric layer over the first etch stop layer and the protection liner;

performing a patterning and removal process to form a cavity in the second interconnect dielectric layer arranged directly over the interconnect wire; and

filling the cavity with a conductive material to form an interconnect via coupled to the interconnect wire.

17. The method of claim 16 , wherein the protection liner comprises graphene.

18. The method of claim 16 further comprising:

forming second etch stop layer on the first etch stop layer and on the protection liner.

19. The method of claim 16 , wherein the first etch stop layer and the protection liner are substantially resistant to removal by the removal process.

20. The method of claim 16 further comprising:

forming a first barrier layer within the cavity, wherein the first barrier layer comprises a material that does not form on the protection liner.