Manufacturing method of a semiconductor memory device

1. A method of manufacturing a semiconductor memory device, the method comprising:

processing a first substrate, wherein processing the first substrate comprises:

disposing a peripheral circuit and a first conductive contact pattern coupled to the peripheral circuit over a first region of the first substrate;

embedding a sacrificial material in a second region of the first substrate; and

disposing a first align mark over the sacrificial material;

processing a second substrate, wherein processing the second substrate comprises disposing a second align mark, a memory cell array, and a second conductive contact pattern coupled to the memory cell array over the second substrate;

orientating the first substrate and the second substrate such that the first conductive contact pattern and the second conductive contact pattern face each other; and

coupling the first conductive contact pattern to the second conductive contact pattern by checking alignment of the first align mark with the second align mark.

2. The method of claim 1 , wherein processing the first substrate comprises:

forming the peripheral circuit at a first surface of the first substrate;

forming a first insulating structure on the first surface of the first substrate to cover the peripheral circuit;

etching the first insulating structure and the second region of the first substrate to form a first groove in the second region of the first substrate;

filling the first groove with the sacrificial material;

forming the first conductive contact pattern coupled to the peripheral circuit and the first align mark disposed over the sacrificial material; and

removing a part of the first substrate from a rear surface of the first substrate opposite the first surface of the first substrate to expose the sacrificial material.

3. The method of claim 2 , further comprising, removing the sacrificial material exposed by removing the part of the first substrate,

wherein checking the alignment of the first align mark with the second align mark comprises checking the alignment through a region from which the sacrificial material was removed.

4. The method of claim 2 , wherein forming the first conductive contact pattern coupled to the peripheral circuit and the first align mark disposed over the sacrificial material comprises:

forming a second insulating structure on the first insulating structure;

forming the first conductive contact pattern coupled to the peripheral circuit and the first align mark contacting the sacrificial material in the second insulating structure;

etching a first part of the second insulating structure to expose an end portion of the first align mark;

removing the end portion of the first align mark such that the first align mark has a shorter length than the first conductive contact pattern; and

etching a second part of the second insulating structure to expose an end portion of the first conductive contact pattern.

5. The method of claim 4 , further comprising:

forming an upper insulating layer over the second substrate, wherein the upper insulating layer has a second groove that exposes the second conductive contact pattern; and

filling the second groove with a conductive adhesive material,

wherein the coupling of the first conductive contact pattern to the second conductive contact pattern comprises:

aligning the end portion of the first conductive contact pattern in the second groove; and

forming a conductive adhesive pattern coupling the first conductive contact pattern to the second conductive contact pattern by heat-curing the conductive adhesive material.

6. The method of claim 1 , wherein processing the second substrate comprises:

forming the memory cell array over the second substrate, wherein the memory cell array includes channel structures that pass through alternately stacked interlayer insulating layers and conductive patterns and includes memory layers that are disposed between the channel structures and the conductive patterns;

forming an insulating structure over the second substrate to cover the memory cell array; and

forming the second conductive contact pattern coupled to the memory cell array, and forming the second align mark over the insulating structure.