Semiconductor device and manufacturing method thereof

1. A method for manufacturing a semiconductor device, comprising:

implanting a substrate;

after implanting the substrate, forming a first patterned mask layer over the substrate, wherein the first patterned mask layer comprises mask portions separated from each other;

depositing an epitaxial layer above the first patterned mask layer and in contact with the substrate;

etching the epitaxial layer, the first patterned mask layer, and the substrate to form at least one semiconductor fin;

forming an isolation structure adjacent the semiconductor fin; and

forming a gate structure above the semiconductor fin and the isolation structure.

2. The method of claim 1 , further comprising forming spacer structures on opposite sidewalls of the mask portions of the first patterned mask layer before depositing the epitaxial layer.

3. The method of claim 2 , further comprising removing the spacer structures after etching the epitaxial layer, the first patterned mask layer, and the substrate.

4. The method of claim 1 , wherein etching the epitaxial layer, the first patterned mask layer, and the substrate comprises:

forming a second patterned mask layer above the epitaxial layer, wherein the second patterned mask layer has at least one opening overlapping one of the mask portions of the first patterned mask layer; and

etching the epitaxial layer, the first patterned mask layer, and the substrate by using the second patterned mask layer as masks.

5. The method of claim 1 , wherein the epitaxial layer and the substrate are made of different materials.

6. The method of claim 1 , wherein the epitaxial layer is spaced apart from top surfaces of the mask portions of the first patterned mask layer.

7. A method for manufacturing a semiconductor device, comprising:

depositing a first epitaxial layer over a substrate;

forming a trench in the first epitaxial layer such that the trench exposes the substrate;

forming a plurality of masks in the trench and on the substrate, wherein top surfaces of the plurality of masks are lower than a top surface of the first epitaxial layer;

depositing a second epitaxial layer over the plurality of masks and in the trench;

patterning the second epitaxial layer, the plurality of masks, and the substrate to form a fin structure; and

forming a gate structure over the fin structure.

8. The method of claim 7 , further comprising forming spacer structures on opposite sides of the plurality of masks prior to depositing the second epitaxial layer.

9. The method of claim 8 , wherein forming the spacer structures is such that tops of the spacer structures are lower than the top surface of the first epitaxial layer.

10. The method of claim 8 , further comprising removing the spacer structures after patterning the second epitaxial layer, the plurality of masks, and the substrate.

11. The method of claim 7 , wherein remaining portions of the plurality of masks remain on sidewalls of the fin structure, and the method further comprises removing the remaining portions of the plurality of masks after patterning the second epitaxial layer, the plurality of masks, and the substrate.

12. The method of claim 11 , further comprising forming an isolation structure on sidewalls of the fin structure after removing the remaining portions of the plurality of masks.

13. The method of claim 7 , wherein forming the plurality of masks is such that at least one of the plurality of masks is in contact with the first epitaxial layer.

14. A method for manufacturing a semiconductor device, comprising:

depositing a first epitaxial layer over a substrate;

forming a trench in the first epitaxial layer;

forming a dielectric structure in the trench of the first epitaxial layer;

depositing a second epitaxial layer over the substrate and in the trench of the first epitaxial layer such that a void is defined by the second epitaxial layer and the dielectric structure;

patterning the first epitaxial layer, the second epitaxial layer, the dielectric structure, and the substrate to form a first fin structure comprising a portion of the first epitaxial layer and a portion of the substrate and a second fin structure comprising a portion of the second epitaxial layer and another portion of the substrate; and

forming a gate structure to cover the first and second fin structures.

15. The method of claim 14 , further comprising forming an isolation structure laterally surrounding the first and second fin structures.

16. The method of claim 15 , wherein forming the isolation structure is such that the isolation structure is in contact with a top surface of the portion of the substrate of the second fin structure and is spaced apart from a top surface of the portion of the substrate of the first fin structure.

17. The method of claim 14 , wherein patterning the first epitaxial layer, the second epitaxial layer, the dielectric structure, and the substrate is such that a bottom of the portion of the second epitaxial layer of the second fin structure tapers downwards.

18. The method of claim 14 , wherein patterning the first epitaxial layer, the second epitaxial layer, the dielectric structure, and the substrate is such that a bottom of the portion of the first epitaxial layer of the first fin structure has a substantially straight sidewall.

19. The method of claim 14 , wherein the second epitaxial layer has a facet at a sidewall of the void.

20. The method of claim 14 , wherein a thickness of the dielectric structure is in a range of about 2 nm to about 20 nm.