IP Library › Granted Patent US 11,309,842

Granted Patent B2

US 11,309,842 · App. 17/017,184 · Granted Apr 19, 2022

Power amplifier circuit

Inventors: Yuri Honda (Kyoto, JP); Hisanori Namie (Kyoto, JP); Hideyuki Satou (Kyoto, JP); Yoshiaki Sukemori (Kyoto, JP)

Assignee: MURATA MANUFACTURING CO., LTD.

H03F1/0205 H03F1/56 H03F3/211 H03F2200/222 H03F2200/387

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Quick Facts

Patent No.: US 11,309,842
App. No.: 17/017,184
Granted: Apr 19, 2022
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A power amplifier circuit includes a first path and a second path between an input terminal and an output terminal, a first amplifier located in the first path operative in a first mode, a second amplifier located in the second path operative in a second mode, a first matching circuit between the first amplifier and the output terminal in the first path, a first capacitor having a first end connected to the output terminal side of the first matching circuit, and a second end, a first inductor having a first end connected to the second end of the first capacitor and a second end grounded, and a short-circuit switch connected in parallel with the first inductor. The short-circuit switch short-circuits the first and second ends of the first inductor in the first mode and is placed in an open-circuit position in the second mode.

Claims (61)

1. A power amplifier circuit comprising:

an input terminal;

an output terminal;

a first path between the input terminal and the output terminal;

a second path between the input terminal and the output terminal, the second path being connected in parallel with the first path;

a first amplifier in the first path, the first amplifier being operative when the power amplifier circuit is in a first mode;

a second amplifier in the second path, the second amplifier being operative when the power amplifier circuit is in a second mode;

a first matching circuit in the first path, the first matching circuit being located between the first amplifier and the output terminal;

a first capacitor, the first capacitor having a first end and a second end, the first end of the first capacitor being connected to the first path between the first matching circuit and the output terminal;

a first inductor having a first end connected to the second end of the first capacitor and a second end that is grounded; and

a short-circuit switch connected in parallel with the first inductor,

wherein the short-circuit switch is configured to be in a short-circuit state when the power amplifier circuit is in the first mode, such that the first and second ends of the first inductor are short-circuited in the short-circuited state, and is configured to be in an open-circuit state when the power amplifier circuit is in the second mode.

2. The power amplifier circuit according to claim 1 , further comprising:

a second matching circuit in the second path, the second matching circuit being located between the second amplifier and the output terminal.

3. The power amplifier circuit according to claim 1 , further comprising:

a third matching circuit in the first path, the third matching circuit being located between the first end of the first capacitor and the output terminal.

4. The power amplifier circuit according to claim 1 , further comprising:

a second matching circuit in the second path, the second matching circuit being located between the second amplifier and the output terminal; and

a third matching circuit in the first path, the third matching circuit being located between the first end of the first capacitor and the output terminal.

5. The power amplifier circuit according to claim 1 , further comprising a switch circuit, the switch circuit comprising:

a first switch between the input terminal and the first amplifier, and

a second switch between the input terminal and the second amplifier, wherein:

the first switch is configured to be in an on state when the power amplifier circuit is in the first mode, such that the input terminal is electrically connected to the first amplifier, and is configured to be in an off state when the power amplifier circuit is in the second mode, such that the input terminal is electrically disconnected from the first amplifier, and

the second switch is configured to be in an on state when the power amplifier circuit is in the second mode, such that the input terminal is electrically connected to the second amplifier, and is configured to be in an off state when the power amplifier circuit is in the first mode, such that the input terminal is electrically disconnected from the second amplifier.

6. The power amplifier circuit according to claim 2 , further comprising a switch circuit, the switch circuit comprising:

a first switch between the input terminal and the first amplifier, and

a second switch between the input terminal and the second amplifier, wherein:

7. The power amplifier circuit according to claim 3 , further comprising a switch circuit, the switch circuit comprising:

a first switch between the input terminal and the first amplifier, and

a second switch between the input terminal and the second amplifier, wherein:

8. The power amplifier circuit according to claim 1 , wherein the first path has a greater gain than the second path.

9. The power amplifier circuit according to claim 2 , wherein the first path has a greater gain than the second path.

10. The power amplifier circuit according to claim 3 , wherein the first path has a greater gain than the second path.

11. The power amplifier circuit according to claim 4 , wherein the first path has a greater gain than the second path.

12. The power amplifier circuit according to claim 1 , wherein:

when the power amplifier circuit is in the first mode, the second amplifier has a capacitive load, and an impedance in the second path as seen from a node between the output terminal and the first and second amplifiers is greater than an impedance as seen from the node at a frequency at which the first amplifier is configured to operate, and

when the power amplifier circuit is in the second mode, the first amplifier has a capacitive load, and an impedance in the first path as seen from the node is greater than an impedance as seen from the node at a frequency at which the second amplifier is configured to operate.

13. The power amplifier circuit according to claim 12 , wherein the first inductor has an inductance value such that that when the power amplifier circuit is in the second mode, the impedance in the first path as seen from the node is high relative to the impedance in the second path.

14. The power amplifier circuit according to claim 12 , wherein when the power amplifier circuit is in the first mode, the impedance in the second path as seen from the node is high relative to the impedance in the first path.

15. The power amplifier circuit according to claim 2 , wherein:

16. The power amplifier circuit according to claim 3 , wherein:

17. The power amplifier circuit according to claim 4 , wherein:

18. The power amplifier circuit according to claim 5 , wherein:

19. The power amplifier circuit according to claim 6 , wherein:

20. The power amplifier circuit according to claim 7 , wherein:

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2020

From: HONDA, YURI; NAMIE, HISANORI; SATOU, HIDEYUKI; SUKEMORI, YOSHIAKI

To: MURATA MANUFACTURING CO., LTD.

Reel/Frame 053738/0687 →

Priority Claims (1)

JP JP2019-165750 · Sep 11, 2019 · national

Continuity (1)

Related Publication 20210075369A1 · Mar 11, 2021

Cited By (1)

US 12,609,661