Electrode agnostic, supply variant stimulation engine for implantable neural stimulation
View Patent ↗Many embodiments of the invention provide a neuromodulation system that includes a digital control unit (DCU) that activates a stimulation engine during active stimulation, a current mirror that includes two feedback loops including a first feedback loop with positive feedback (PF) made of an error amplifier A 1 and transistors M 3 and M 1 and a second feedback loop with a negative feedback (NF) made of the error amplifier A 1 and transistor M 3 , and a high-voltage adaptive rail (V dd /V ss ) to accommodate voltage drops across high electrode impedances.
1. An integrated circuit comprising,
a multi-channel stimulation and sensing unit comprising a plurality of electrode contacts that provide concurrent stimulation and sensing;
an on-chip power management unit;
an on-chip electrode agnostic stimulation engine circuitry comprising:
a digital control unit (DCU) that activates the electrode agnostic stimulation engine during active stimulation;
a current mirror comprising two feedback loops including a first feedback loop with positive feedback (PF) and a second feedback loop with a negative feedback (NF); and
a high-voltage adaptive rail (V DD /V SS ) to accommodate voltage drops across high electrode impedances, wherein when the at least one contact is stimulating with a particular current level, the DCU configures an output of the high-voltage adaptive rail to produce stimulation power supplies V DD and V SS according to the at least one electrode contact impedance.
2. The integrated circuit of claim 1 , wherein the first feedback loop with positive feedback comprises an error amplifier A 1 and transistors M 3 and M 1 .
3. The integrated circuit of claim 2 , wherein the second feedback loop with negative feedback comprises the error amplifier A 1 and transistor M 3 .
4. The integrated circuit of claim 1 , further comprising adaptive closed-loop 4-stage charge pumps that provides supply rails V DD /V SS .
5. The integrated circuit of claim 1 , wherein the PF is synchronized with an input signal and is determined as a positive loop gain (LF) within a feedback loop.
6. The integrated circuit of claim 1 , further comprising an extra NF that includes another operation amplifier A 2 , wherein a plus terminal of amplifier A 2 is attached to a bias voltage, V B to facilitate the V out swing increase of the mirror by shielding the input of A 1 .
7. The integrated circuit of claim 1 , further comprising cascode PMOS/NMOS amplifiers that control voltage-levels close to V DD /V SS .
8. The integrated circuit of claim 1 , further comprising:
a local switch matrix (LSM) for biphasic control and post-stimulation active charge balancing.
9. The integrated circuit of claim 1 , wherein the DCU configures an output of high voltage generators to produce stimulation power supplies V DD and V SS .