Semiconductor memory device
A memory cell of a 2-port static random access memory (SRAM) includes first and second p-type transistors and first to sixth n-type transistors. Gate interconnects extend in the X direction and are arranged in three rows in the Y direction. The gate interconnects in the first row form gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor, the gate interconnect in the second row forms gates of the fifth and sixth n-type transistors, and the gate interconnects in the third row form gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor.
1. A semiconductor memory device, comprising:
a memory cell;
a first word line extending in a first direction;
a first bit line pair constituted by a first main bit line and a first sub-bit line extending in a second direction perpendicular to the first direction;
a second word line extending in the second direction; and
a second bit line pair constituted by a second main bit line and a second sub-bit line extending in the first direction,
wherein the memory cell includes:
a first inverter including a first p-type transistor and a first n-type transistor connected in series, an input of the first inverter being connected with a first node and an output connected with a second node,
a second inverter including a second p-type transistor and a second n-type transistor connected in series, an input of the second inverter being connected with the second node and an output connected with the first node,
a third n-type transistor connected between the first main bit line and the first node, having a gate connected with the first word line,
a fourth n-type transistor connected between the first sub-bit line and the second node, having a gate connected with the first word line,
a fifth n-type transistor connected between the second main bit line and the first node, having a gate connected with the second word line, and
a sixth n-type transistor connected between the second sub-bit line and the second node, having a gate connected with the second word line,
gate interconnects that are to be gates of the first and second p-type transistors and the first to sixth n-type transistors extend in the first direction and are arranged in three rows in the second direction,
the gate interconnects in the first row form the gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor,
the gate interconnect in the second row forms the gates of the fifth and sixth n-type transistors, and
the gate interconnects in the third row form the gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor.
2. A semiconductor memory device, comprising:
a memory cell;
a first word line extending in a first direction;
a first bit line pair constituted by a first main bit line and a first sub-bit line extending in a second direction perpendicular to the first direction;
a second word line; and
a second bit line pair constituted by a second main bit line and a second sub-bit line,
wherein the memory cell includes:
a first inverter including a first p-type transistor and a first n-type transistor connected in series, an input of the first inverter being connected with a first node and an output connected with a second node,
a second inverter including a second p-type transistor and a second n-type transistor connected in series, an input of the second inverter being connected with the second node and an output connected with the first node,
a third n-type transistor connected between the first main bit line and the first node, having a gate connected with the first word line,
a fourth n-type transistor connected between the first sub-bit line and the second node, having a gate connected with the first word line,
a fifth n-type transistor connected between the second main bit line and the first node, having a gate connected with the second word line, and
a sixth n-type transistor connected between the second sub-bit line and the second node, having a gate connected with the second word line,
gate interconnects that are to be gates of the first and second p-type transistors and the first to sixth n-type transistors extend in the first direction and are arranged in three rows in the second direction,
the gate interconnects in the first row form the gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor,
the gate interconnect in the second row forms the gates of the fifth and sixth n-type transistors,
the gate interconnects in the third row form the gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor, and
the memory cell is connected with the first word line through a via formed at an end of the memory cell in the first direction, and is connected with the first main bit line and the first sub-bit line through vias formed at ends of the memory cell in the second direction.
3. A semiconductor memory device, comprising:
a memory cell;
a first word line;
a first bit line pair constituted by a first main bit line and a first sub-bit line;
a second word line; and
a second bit line pair constituted by a second main bit line and a second sub-bit line,
wherein the memory cell includes:
a first inverter including a first p-type transistor and a first n-type transistor connected in series, an input of the first inverter being connected with a first node and an output connected with a second node,
a second inverter including a second p-type transistor and a second n-type transistor connected in series, an input of the second inverter being connected with the second node and an output connected with the first node,
a third n-type transistor connected between the first main bit line and the first node, having a gate connected with the first word line,
a fourth n-type transistor connected between the first sub-bit line and the second node, having a gate connected with the first word line,
a fifth n-type transistor connected between the second main bit line and the first node, having a gate connected with the second word line, and
a sixth n-type transistor connected between the second sub-bit line and the second node, having a gate connected with the second word line,
gate interconnects that are to be gates of the first and second p-type transistors and the first to sixth n-type transistors extend in a first direction and are arranged in three rows in a second direction perpendicular to the first direction,
the gate interconnects in the first row form the gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor,
the gate interconnect in the second row forms the gates of the fifth and sixth n-type transistors,
the gate interconnects in the third row form the gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor,
the fourth n-type transistor is located on a first-hand side in the first direction with respect to the first n-type transistor and the first p-type transistor, and
the third n-type transistor is located on a second-hand side in the first direction with respect to the second n-type transistor and the second p-type transistor, the second-hand side being the side opposite to the first-hand side.