Epitaxial blocking layer for multi-gate devices and fabrication methods thereof

1. A method, comprising:

providing a silicon substrate;

doping a top portion of the silicon substrate;

epitaxially growing a dopant blocking layer from a top surface of the silicon substrate, wherein the dopant blocking layer has a lattice constant different from the silicon substrate;

epitaxially growing an undoped silicon layer from a top surface of the dopant blocking layer;

epitaxially growing a semiconductor stack of alternating first and second semiconductor layers from a top surface of the undoped silicon layer, wherein the undoped silicon layer serves as a lattice buffering layer with a lattice constant between those of the dopant blocking layer and a bottommost semiconductor layer of the semiconductor stack;

patterning the semiconductor stack to form a semiconductor fin;

forming a source/drain (S/D) feature in contact with the semiconductor fin; and

forming a gate structure engaging the semiconductor fin.

2. The method of claim 1 , wherein the lattice constant of the dopant blocking layer is smaller than that of the silicon substrate.

3. The method of claim 1 , wherein a lower portion of the dopant blocking layer is a polycrystalline layer and an upper portion of the dopant blocking layer is a crystalline layer.

4. The method of claim 1 , wherein the forming of the dopant blocking layer includes applying a hydrogen and a carbon-containing precursor at a first temperature followed by applying the carbon-containing precursor and a silicon-containing precursor at a second temperature that is higher than the first temperature.

5. The method of claim 4 , wherein the carbon-containing precursor includes ethylene and the silicon-containing precursor includes trichlorosilane.

6. The method of claim 1 , wherein the dopant blocking layer includes a material selected from the group of SiP, SiAs, SiCP, and SiC.

7. The method of claim 1 , wherein a lattice constant of the undoped silicon layer is larger than the lattice constant of the dopant blocking layer.

8. The method of claim 1 , wherein the undoped silicon layer has a thickness not less than about 20 nm and the dopant blocking layer has a thickness ranging from about 2 nm to about 5 nm.

9. The method of claim 1 , wherein the forming of the S/D feature includes:

recessing a portion of the semiconductor fin, thereby exposing the dopant blocking layer;

removing a portion of the dopant blocking layer, thereby exposing the silicon substrate; and

epitaxially growing the S/D feature from the silicon substrate.

10. The method of claim 1 , further comprising:

forming a spacer feature interposing between the S/D feature and the gate structure, wherein a bottommost portion of the spacer feature has a first length measured along a lengthwise direction of the semiconductor fin, wherein a topmost portion of the spacer feature has a second length measured along the lengthwise direction of the semiconductor fin, and wherein a ratio of the first length over the second length ranges from about 1.05:1 to about 1.2:1.

11. A method of manufacturing a multi-gate device, comprising:

providing a semiconductor substrate;

doping a top portion of the semiconductor substrate;

forming a dopant blocking layer in contact with the semiconductor substrate, wherein the dopant blocking layer has a higher resistance than the semiconductor substrate;

forming a buffer layer above and in contact with the dopant blocking layer, wherein the buffer layer has a lower resistance than the dopant blocking layer;

after the forming of the buffer layer, forming a plurality of semiconductor nanosheets directly above the buffer layer;

forming an epitaxial source/drain (S/D) feature in contact with the plurality of semiconductor nanosheets; and

forming a gate structure wrapping each of the plurality of semiconductor nanosheets.

12. The method of claim 11 , wherein the dopant blocking layer has a higher thermal conductivity and a lower coefficient of thermal expansion than the semiconductor substrate and the buffer layer.

13. The method of claim 11 , wherein the buffer layer and the plurality of semiconductor nanosheets include a same material composition.

14. The method of claim 11 , wherein the dopant blocking layer has a thickness ranging from about 2 nm to about 5 nm.

15. The method of claim 11 , wherein a thickness of the buffer layer is not less than about 20 nm.

16. The method of claim 11 , wherein the epitaxial S/D feature is directly above the dopant blocking layer.

17. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming a blocking layer above the semiconductor substrate, wherein the blocking layer includes a material composition selected from the group of SiP, SiAs, and SiCP;

forming a buffer layer above the blocking layer, wherein the buffer layer includes a material composition different from the blocking layer;

forming a semiconductor layer above the buffer layer, wherein the semiconductor layer includes a material composition different from the blocking layer and the buffer layer;

patterning the semiconductor layer and the buffer layer to form a fin-shaped structure;

etching the fin-shaped structure and the blocking layer in a source/drain (S/D) region, thereby forming an S/D trench and exposing the semiconductor substrate in the S/D trench; and

epitaxially growing an S/D feature in the S/D trench, wherein the S/D feature adjoins the fin-shaped structure, and wherein a bottom surface of the S/D feature is below a bottom surface of the blocking layer.

18. The method of claim 17 , wherein the buffer layer is thicker than the blocking layer.

19. The method of claim 17 , further comprising:

depositing an isolation feature on sidewalls of the blocking layer and the buffer layer, wherein a top surface of the isolation feature is above a top surface of the blocking layer but below a top surface of the buffer layer.

20. The method of claim 17 , wherein the buffer layer includes undoped silicon.