Two-dimensional vertical fins
View Patent ↗A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate.
1. A method of forming a vertical fin having multiple arms, comprising:
heat treating a periodic array of openings having an irregular shape in a substrate, wherein walls of substrate material are disposed between adjacent openings to reduce the surface area of the openings; and
etching the openings with a crystal-plane selective etch to form squared openings in the substrate.
2. The method of claim 1 , further comprising, forming a mask over a plurality of squared openings and at least a portion of the walls between the squared openings that intersect.
3. The method of claim 2 , further comprising, removing the portions of the substrate and walls not covered by the mask to form a two-dimensional vertical fin on the substrate.
4. The method of claim 3 , wherein the two-dimensional vertical fin has a shape selected from the group consisting of a cross shape, an H-shape, a fence shape, and a lattice-shape.
5. The method of claim 1 , wherein the periodic array of irregular openings is arranged as a square lattice, a rectangular lattice, a hexagonal lattice with vertical columns, or a hexagonal lattice with horizontal rows.
6. The method of claim 5 , wherein the periodic array of openings having the irregular shape is arranged as a rectangular lattice having walls with different thicknesses between horizontally adjacent openings than vertically adjacent openings.
7. The method of claim 1 , wherein the heat treating is selected from the group consisting of a furnace anneal, a rapid thermal anneal (RTA), a flash anneal, a laser anneal, or a combination thereof.
8. The method of claim 7 , wherein the heat treating is conducted at a temperature in a range of about 400° C. to about 1200° C.
9. The method of claim 7 , wherein the heat treating is conducted for a duration in a range of about 5 seconds (sec) to about 30 minutes (min).
10. The method of claim 7 , wherein the heat treating is conducted in an atmosphere including a reducing gas selected from the group consisting of hydrogen gas (H 2 ), deuterium (D 2 ), and combinations thereof.
11. A method of forming a vertical fin having multiple arms, comprising:
forming a periodic array of openings having an irregular shape in a substrate, wherein walls of substrate material are disposed between adjacent openings;
heat treating the substrate and openings to reduce the surface area of the openings; and
etching the openings with a crystal-plane selective etch to form squared openings in the substrate.
12. The method of claim 11 , wherein the substrate material is a semiconductor material selected from the group consisting of single crystal silicon (c-Si), silicon-germanium (SiGe), and germanium (Ge), and a {110} crystal plane of the substrate material is selectively etched.
13. The method of claim 12 , wherein the crystal-plane selective etch is a wet etch using ammonium hydroxide (NH 3 OH) or a gas etch using hydrogen chloride (HCl).
14. The method of claim 11 , wherein the substrate material is a III-V semiconductor material and a {111} crystal plane of the substrate material is selectively etched.
15. A two-dimensional vertical fin field effect transistor device, comprising:
a two-dimensional vertical fin having intersecting arms with square corners where perpendicular crystal planes meet.
16. The two-dimensional vertical fin field effect transistor device of claim 15 , wherein the two-dimensional vertical fin is a semiconductor material selected from the group consisting of single crystal silicon (c-Si), silicon-germanium (SiGe), and germanium (Ge).
17. The two-dimensional vertical fin field effect transistor device of claim 15 , wherein the perpendicular crystal planes are {110} and {−110}, and the square corners are atomically sharp.
18. The two-dimensional vertical fin field effect transistor device of claim 15 , wherein the each of the intersecting arms has a thickness in a range of about 5 nm to about 20 nm.
19. The two-dimensional vertical fin field effect transistor device of claim 15 , further comprising a top source/drain on the two-dimensional vertical fin, wherein the top source/drain has the same two-dimensional shape as the two-dimensional vertical fin.
20. The two-dimensional vertical fin field effect transistor device of claim 19 , further comprising a bottom source/drain adjoining a side of the two-dimensional vertical fin opposite the top source/drain.