Uniform gate width for nanostructure devices
According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
1. A semiconductor device comprising:
a substrate;
a fin stack comprising:
a plurality of nanostructures;
a gate device surrounding each of the nanostructures, a thickness of each gate device differs between different layers of the fin stack;
inner spacers along the gate device and between the nanostructures, wherein a width of the inner spacers differs between different layers of the fin stack.
2. The semiconductor device of claim 1 , further comprising gate regions between the plurality of nanostructures, the gate regions varying in depth by layer.
3. The semiconductor device of claim 2 , wherein variation by layer is within a range of 2-12 nanometers.
4. The semiconductor device of claim 1 , wherein the inner spacers comprise at least one of: SiCN, SiOCN, and SiON.
5. The semiconductor device of claim 1 , wherein the inner spacers vary by layer within a range of about 4-15 nanometers with respect to a width for each sidewall spacer.
6. The semiconductor device of claim 1 , wherein channel length of each nanostructure is substantially uniform.
7. The semiconductor device of claim 1 , wherein the thickness of each gate device increases closer to the substrate.
8. A semiconductor device comprising:
a substrate;
a transistor device comprising:
two source/drain regions;
a fin stack having a plurality of channel features extending between the two source/drain regions;
a gate feature surrounding the plurality of channel features so as to include a plurality of gate regions between each of the channel features; and
sidewall spacers along sidewalls of the gate feature and between the channel features;
wherein a width of each of the gate regions between the channel features is substantially uniform and wherein a thickness of the gate regions varies by layers.
9. The semiconductor device of claim 8 , wherein variation by layer is within a range of 2-12 nanometers.
10. The semiconductor device of claim 8 , wherein channel length of each channel feature is substantially uniform.
11. The semiconductor device of claim 8 , wherein the sidewall spacers comprise at least one of: SiCN, SiOCN, and SiON.
12. The semiconductor device of claim 8 , wherein the thickness of the gate regions increases closer to the substrate.
13. A method for fabricating a semiconductor device, the method comprising:
depositing alternating layers of a first semiconductor material and a second semiconductor material on a substrate, the first semiconductor material being a sacrificial material and the second semiconductor material comprising a channel material, wherein each layer of the first semiconductor material varies in characteristics;
performing a patterning process to form a fin stack;
partially laterally etching the first semiconductor material from the fin stack such that a width of remaining portions of the first semiconductor material is substantially uniform; and
forming inner spacers on each of the remaining portions of the first semiconductor material such that a width of sidewall spacers increases towards the substrate; and
forming a gate structure around each second semiconductor material such that a thickness of the gate structure between each second semiconductor material increases closer to the substrate.
14. The method of claim 13 , further comprising, removing the remaining portions of the first semiconductor material.
15. The method of claim 13 , wherein a width of the gate structure in each of the layers is substantially uniform.
16. The method of claim 13 , wherein the first semiconductor material comprises silicon germanium.
17. The method of claim 16 , wherein a concentration of germanium in each layer of the fin stack increases towards the substrate.
18. The method of claim 17 , wherein the concentration varies between about 5-50 percent.
19. The method of claim 13 , wherein the first semiconductor material is a composite semiconductor material.
20. The method of claim 13 , wherein each first semiconductor material of the alternating layers has a different concentration of germanium.