Solid state image device having an impurity concentration at a p/n interface of one photodiode being equal to or greater than at p/n interface of another photodiode within a semiconductor substrate
A solid-state imaging device includes: a first photodiode made up of a first first-electroconductive-type semiconductor region formed on a first principal face side of a semiconductor substrate, and a first second-electroconductive-type semiconductor region formed within the semiconductor substrate adjacent to the first first-electroconductive-type semiconductor region; a second photodiode made up of a second first-electroconductive-type semiconductor region formed on a second principal face side of the semiconductor substrate, and a second second-electroconductive-type semiconductor region formed within the semiconductor substrate adjacent to the second first-electroconductive-type semiconductor region; and a gate electrode formed on the first principal face side of the semiconductor substrate; with impurity concentration of a connection face between the second first-electroconductive-type semiconductor region and the second second-electroconductive-type semiconductor region being equal to or greater than impurity concentration of a connection face of an opposite layer of the second first-electroconductive-type semiconductor region of the second second-electroconductive-type semiconductor region.
1. A solid-state imaging device, comprising:
a semiconductor substrate;
a first photodiode including:
a first semiconductor region of a first-electroconductive-type, on a first principal side of said semiconductor substrate;
a second semiconductor region of a second-electroconductive-type, within said semiconductor substrate, wherein said second semiconductor region is in contact with a first surface of said first semiconductor region; and
a third semiconductor region of said second-electroconductive-type, within said semiconductor substrate, wherein said third semiconductor region is adjacent to said second semiconductor region;
a second photodiode including:
a fourth semiconductor region of said first-electroconductive-type, on a second principal side of said semiconductor substrate, wherein
said fourth semiconductor region is configured to suppress dark current in said second photodiode,
said second principal side is a light receiving side of said semiconductor substrate, and
said first semiconductor region and said fourth semiconductor region have a same planar area;
a fifth semiconductor region of said second-electroconductive-type, within said semiconductor substrate, wherein a first surface of said fourth semiconductor region is in contact with said fifth semiconductor region; and
a sixth semiconductor region of said second-electroconductive-type, within said semiconductor substrate, wherein
said sixth semiconductor region is between said fifth semiconductor region and said third semiconductor region, and
said third semiconductor region of said first photodiode and said sixth semiconductor region of said second photodiode are connected at a center of said semiconductor substrate;
a gate electrode on said first principal side of said semiconductor substrate;
a vertical-type transfer transistor on said first principal side of said semiconductor substrate, wherein
said vertical-type transfer transistor is configured to read out charges from said first photodiode and said second photodiode,
said vertical-type transfer transistor does not overlap said first photodiode and said second photodiode in a plan view of said solid-state imaging device, and
a first impurity concentration of said fifth semiconductor region at a first connection face between said fourth semiconductor region and said fifth semiconductor region is equal to or greater than a second impurity concentration of said sixth semiconductor region at a second connection face between said third semiconductor region and said sixth semiconductor region;
a first insulating layer on said first principal side of said semiconductor substrate;
a wiring layer in contact with a first surface of said first insulating layer;
a second insulating layer on said second principal side of said semiconductor substrate, wherein
an entirety of a second surface of said fourth semiconductor region is in contact with said second insulating layer, and
said first surface of said fourth semiconductor region is opposite to said second surface of said fourth semiconductor region;
a first pixel separation portion, wherein
an entirety of a first surface of said first pixel separation portion is in contact with a second surface of said first insulating layer,
an entirety of a second surface of said first semiconductor region is in contact with said second surface of said first insulating layer,
said first surface of said first semiconductor region is opposite to said second surface of said first semiconductor region, and
said first surface of said first insulating layer is opposite to said second surface of said first insulating layer; and
a second pixel separation portion, wherein
an entirety of a first surface of said second pixel separation portion is in contact with said second insulating layer,
said first surface of said second pixel separation portion is opposite to said first surface of said first pixel separation portion,
a second surface of said first pixel separation portion and a second surface of said second pixel separation portion are connected at said center of said semiconductor substrate, and
said first pixel separation portion and said second pixel separation portion are adjacent to said vertical-type transfer transistor.
2. The solid-state imaging device according to claim 1 , wherein
a third impurity concentration of said third semiconductor region is lower than a fourth impurity concentration of said second semiconductor region, and
a fifth impurity concentration of said fifth semiconductor region is greater than a sixth impurity concentration of said sixth semiconductor region.
3. An electronic device, comprising:
a solid-state imaging device including:
a semiconductor substrate;
an imaging unit that includes:
a first photodiode including:
a first semiconductor region of a first-electroconductive-type, on a first principal side of said semiconductor substrate;
a second semiconductor region of a second-electroconductive-type, within said semiconductor substrate, wherein said second semiconductor region is in contact with a first surface of said first semiconductor region; and
a third semiconductor region of said second-electroconductive-type, within said semiconductor substrate, wherein said third semiconductor region is adjacent to said second semiconductor region;
a second photodiode including:
a fourth semiconductor region of said first-electroconductive-type, on a second principal side of said semiconductor substrate, wherein
said fourth semiconductor region is configured to suppress dark current in said second photodiode,
said second principal side is a light receiving side of said semiconductor substrate, and
said first semiconductor region and said fourth semiconductor region have a same planar area;
a fifth semiconductor region of said second-electroconductive-type, within said semiconductor substrate, wherein a first surface of said fourth semiconductor region is in contact with said fifth semiconductor region; and
a sixth semiconductor region of said second-electroconductive-type, within said semiconductor substrate, wherein
said sixth semiconductor region is between said fifth semiconductor region and said third semiconductor region, and
said third semiconductor region of said first photodiode and said sixth semiconductor region of said second photodiode are connected at a center of said semiconductor substrate;
a gate electrode on said first principal side of said semiconductor substrate;
a vertical-type transfer transistor on said first principal side of said semiconductor substrate, wherein
said vertical-type transfer transistor is configured to read out charges from said first photodiode and said second photodiode,
said vertical-type transfer transistor does not overlap said first photodiode and said second photodiode in a plan view of said solid-state imaging device, and
a first impurity concentration of said fifth semiconductor region at a first connection face between said fourth semiconductor region and said fifth semiconductor region is equal to or greater than a second impurity concentration of said sixth semiconductor region at a second connection face between said third semiconductor region and said sixth semiconductor region;
a first insulating layer on said first principal side of said semiconductor substrate;
a wiring layer in contact with a first surface of said first insulating layer;
a second insulating layer on said second principal side of said semiconductor substrate, wherein
an entirety of a second surface of said fourth semiconductor region is in contact with said second insulating layer, and
said first surface of said fourth semiconductor region is opposite to said second surface of said fourth semiconductor region;
a first pixel separation portion, wherein
an entirety of a first surface of said first pixel separation portion is in contact with a second surface of said first insulating layer,
an entirety of a second surface of said first semiconductor region is in contact with said second surface of said first insulating layer,
said first surface of said first semiconductor region is opposite to said second surface of said first semiconductor region, and
said first surface of said first insulating layer is opposite to said second surface of said first insulating layer; and
a second pixel separation portion, wherein
an entirety of a first surface of said second pixel separation portion is in contact with said second insulating layer,
said first surface of said second pixel separation portion is opposite to said first surface of said first pixel separation portion,
a second surface of said first pixel separation portion and a second surface of said second pixel separation portion are connected at said center of said semiconductor substrate, and
said first pixel separation portion and said second pixel separation portion are adjacent to said vertical-type transfer transistor;
an optical system configured to guide incident light into said imaging unit; and
a signal processing circuit configured to process an output signal of said solid-state imaging device.