IP Library Granted Patent US 11,315,992
Granted Patent B2
US 11,315,992 · App. 16/957,369 · Granted Apr 26, 2022

Array substrate and method for preparing the same, display panel and display device

Inventor: Ying Cui (Beijing, CN)
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
H01L27/3246H01L51/0005H01L51/56H01L2251/558
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Quick Facts
Patent No.
US 11,315,992
App. No.
16/957,369
Granted
Apr 26, 2022
Kind
B2
Abstract

The present disclosure provides an array substrate, including: a base substrate; a planarization layer formed on the base substrate; a plurality of pixel electrodes formed on the planarization layer; and a pixel definition layer including a first pixel definition layer and a second pixel definition layer, the first pixel definition layer covering a periphery of each pixel electrode and exposing a central area of each pixel electrode, the second pixel definition layer being formed on the planarization layer between adjacent pixel electrodes and having a plurality of openings defining each sub-pixel unit; a bottom of a dam portion of the second pixel definition layer and a bottom of a dam portion of the first pixel definition layer adjacent thereto are separated by a predetermined distance, and a thickness of the second pixel definition layer is greater than a thickness of the first pixel definition layer.

Claims (31)

1. A display panel comprising an array substrate, comprising:

a base substrate;

a planarization layer formed on the base substrate;

a plurality of pixel electrodes formed on the planarization layer; and

a pixel definition layer comprising a first pixel definition layer and a second pixel definition layer, the first pixel definition layer covering a periphery of each of the plurality of pixel electrodes and exposing a central area of each of the plurality of pixel electrodes, the second pixel definition layer being formed on the planarization layer between adjacent pixel electrodes and having a plurality of openings defining each sub-pixel unit; a bottom of a dam portion of the second pixel definition layer and a bottom of a dam portion of the first pixel definition layer adjacent thereto are separated by a predetermined distance, and a thickness of the second pixel definition layer is greater than a thickness of the first pixel definition layer,

wherein a width of the first pixel definition layer covering the periphery of each of the plurality of pixel electrodes is 1 μm to 10 μm;

wherein the plurality of openings of the second pixel defining layer is formed with an organic light-emitting layer of each sub-pixel unit, a thickness of the organic light-emitting layer being greater than a thickness of the first pixel definition layer;

wherein the organic light-emitting layer is in direct contact with a side wall of the second pixel definition layer; and

wherein the predetermined distance is configured to allow an ink forming the organic light-emitting layer have a Marangoni reflow effect occur in an area between the bottom of the dam portion of the second pixel definition layer and the bottom of a dam portion of the first pixel definition layer adjacent thereto.

2. A display device comprising the display panel of claim 1 .

3. The display panel of claim 1 , wherein the first pixel definition layer has a thickness of 100 nm to 500 nm, and the second pixel definition layer has a thickness of 1 μm to 3 μm.

4. The display panel of claim 1 , wherein the first pixel definition layer comprises one or more of silicon nitride and silicon oxide.

5. The display panel of claim 1 , wherein the second pixel definition layer comprises a photoresist material.

6. A method for preparing an array substrate, comprising:

forming a planarization layer on a base substrate;

forming a plurality of pixel electrodes on the planarization layer;

forming a first pixel definition layer to cover a periphery of each of the plurality of pixel electrodes, the first pixel definition layer exposing a central area of each of the plurality of pixel electrodes; and

forming a second pixel definition layer on the planarization layer between adjacent pixel electrodes, the second pixel definition layer having a plurality of openings defining each sub-pixel unit;

wherein a bottom of a dam portion of the second pixel definition layer and a bottom of a dam portion of the first pixel definition layer adjacent thereto are separated by a predetermined distance, and a thickness of the second pixel definition layer is greater than a thickness of the first pixel definition layer;

wherein a width of the first pixel definition layer covering the periphery of each of the plurality of pixel electrodes is 1 μm to 10 μm;

wherein the plurality of openings of the second pixel defining layer is formed with an organic light-emitting layer of each sub-pixel unit, a thickness of the organic light-emitting layer being greater than a thickness of the first pixel definition layer;

wherein the organic light-emitting layer is in direct contact with a side wall of the second pixel definition layer; and

wherein the predetermined distance is configured to allow an ink forming the organic light-emitting layer have a Marangoni reflow effect occur in an area between the bottom of the dam portion of the second pixel definition layer and the bottom of a dam portion of the first pixel definition layer adjacent thereto.

7. The method of claim 6 , wherein the forming the first pixel definition layer comprises:

forming an insulating dielectric layer covering the planarization layer and the plurality of pixel electrodes; and

etching the insulating dielectric layer to form the first dielectric layer.

8. The method of claim 7 , wherein the insulating dielectric layer comprises one or more of silicon nitride and silicon oxide.

9. The method of claim 6 , wherein the forming the second pixel definition layer comprises:

forming a photoresist material layer covering the planarization layer, the first pixel definition layer, and the plurality of pixel electrodes; and

patterning the photoresist material layer to form the second pixel definition layer.

10. The method of claim 6 , wherein the first pixel definition layer has a thickness of 100 nm to 500 nm, and the second pixel definition layer has a thickness of 1 μm to 3 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2020
From: CUI, YING
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 053043/0432 →
Priority Claims (1)
CN 201910117700.1 · Feb 15, 2019 · national
Continuity (1)
Related Publication 20210175302A1 · Jun 10, 2021
Cited By (1)
US 12,701,871