Integrated circuit device and method of fabricating the same
An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.
1. A semiconductor device comprising:
a substrate;
a first fin disposed on the substrate;
a second fin disposed on the substrate;
an insulation disposed on the substrate, and disposed between the first fin and the second fin;
a first gate disposed on the first fin, the insulation and the second fin;
a second gate disposed on the first fin, the insulation and the second fin;
a first source/drain disposed on the first fin;
a second source/drain disposed on the first fin; and
a fin isolation disposed on the substrate and disposed between the first source/drain and the second source/drain,
wherein the first source/drain is disposed between the first gate and the fin isolation,
the second source/drain is disposed between the second gate and the fin isolation,
no gate is disposed between the first source/drain and the fin isolation, and
no gate is disposed between the second source/drain and the fin isolation.
2. The semiconductor device of claim 1 , wherein the fin isolation includes a lower portion and an upper portion disposed on the lower portion,
the lower portion of the fin isolation includes a first portion, a second portion disposed on the first portion and a third portion disposed on the second portion, and
a width of the second portion of the lower portion of the fin isolation is greater than a width of the first portion of the lower portion of the fin isolation, and greater than a width of the third portion of the lower portion of the fin isolation.
3. The semiconductor device of claim 1 , wherein a minimum width of fin isolation is less than a maximum width of the first gate.
4. The semiconductor device of claim 1 , wherein a distance between a vertical center line of the fin isolation and the first source/drain is less than a width of the first gate.
5. The semiconductor device of claim 1 , wherein a half of a maximum width of the fin isolation is less than a minimum width of the first gate.
6. The semiconductor device of claim 1 , wherein a bottom surface of the fin isolation is disposed lower than a bottom surface of the first gate, and lower than a bottom surface of the first source/drain.
7. The semiconductor device of claim 1 , further comprising a capping layer disposed on the first gate.
8. A semiconductor device comprising:
a substrate;
a first active region disposed on the substrate;
a second active region disposed on the substrate;
an insulation disposed on the substrate, and disposed between the first active region and the second active region;
a first gate disposed on the first active region, the insulation and the second active region;
a second gate disposed on the first active region, the insulation and the second active region;
a first source/drain disposed on the first active region;
a second source/drain disposed on the first active region; and
an isolation disposed on the substrate, and disposed between the first source/drain and the second source/drain,
wherein the first source/drain is disposed between the first gate and the isolation,
the second source/drain is disposed between the second gate and the isolation,
no gate is disposed between the first source/drain and the second source/drain,
the isolation includes a lower portion and an upper portion disposed on the lower portion,
the lower portion of the isolation includes a first portion, a second portion disposed on the first portion and a third portion disposed on the second portion, and
a width of the second portion of the lower portion of the isolation is greater than a width of the first portion of the lower portion of the isolation, and greater than a width of the third portion of the lower portion of the isolation.
9. The semiconductor device of claim 8 , wherein the isolation completely separate the first source/drain and the second source/drain such that a top portion of the first source/drain is separated from a top portion of the second source/drain by the isolation, and a bottom portion of the first source/drain is separated from a bottom portion of the second source/drain by the isolation.
10. The semiconductor device of claim 8 , wherein a sidewall of the lower portion of the isolation includes a rounded portion.
11. The semiconductor device of claim 8 , wherein a sidewall of the lower portion of the isolation includes a convex portion.
12. The semiconductor device of claim 8 , wherein a bottom surface of the isolation is disposed lower than a bottom surface of the first gate, and lower than a bottom surface of the first source/drain.
13. The semiconductor device of claim 8 , further comprising:
a first source/drain contact disposed on the first source/drain;
a second source/drain contact disposed on the second source/drain;
a first gate contact disposed on the first gate, and disposed above the second active region; and
a second gate contact disposed on the second gate, and disposed above the second active region.
14. The semiconductor device of claim 8 , wherein the isolation includes an ion implantation region.
15. A semiconductor device comprising:
a substrate;
a first fin disposed on the substrate;
a second fin disposed on the substrate;
an insulation disposed on the substrate, and disposed between the first fin and the second fin;
a first gate disposed on the first fin, the insulation and the second fin;
a second gate disposed on the first fin, the insulation and the second fin;
a first source/drain disposed on the first fin;
a second source/drain disposed on the first fin;
a first source/drain contact disposed on the first source/drain;
a second source/drain contact disposed on the second source/drain; and
a fin isolation disposed on the substrate, and disposed between the first source/drain and the second source/drain,
wherein the first source/drain is disposed between the first gate and the fin isolation,
the second source/drain is disposed between the second gate and the fin isolation,
no gate is disposed between the first gate and the second gate, and
a sidewall of the fin isolation includes a convex portion.
16. The semiconductor device of claim 15 , wherein a width of an upper portion of the first source/drain is greater than a width of a lower portion of the first source/drain.
17. The semiconductor device of claim 15 , wherein the first source/drain contact includes Co, Cu, W, Ru, Mn, Ti, Ta, TiN or TaN.
18. The semiconductor device of claim 15 , further comprising:
a first gate contact disposed on the first gate; and
a second gate contact disposed on the second gate.
19. The semiconductor device of claim 18 , wherein each of the first gate contact and the second gate contact is above the second fin.
20. The semiconductor device of claim 15 , wherein the fin isolation includes a lower portion and an upper portion disposed on the lower portion,
the lower portion of the fin isolation includes a first portion, a second portion disposed on the first portion and a third portion disposed on the second portion, and
a width of the second portion of the lower portion of the fin isolation is greater than a width of the first portion of the lower portion of the fin isolation, and greater than a width of the third portion of the lower portion of the fin isolation.