BCE IGZO TFT device and manufacturing method thereof
A BCE IGZO TFT device and a manufacturing method thereof include steps of providing a substrate, depositing a first metal layer on the substrate, wherein the first metal layer forms a gate and a first electrode layer by a patterning process, depositing a gate insulating layer on the substrate, the gate, and the first electrode layer, wherein the gate insulating layer is etched to remove a part of the gate insulating layer on a surface of the first electrode layer, depositing an active layer on the first electrode layer and the gate insulating layer, wherein the active layer and the first electrode layer are in direct contact, and depositing a second metal layer on the active layer, wherein the second metal layer forms a source, a drain, and a second electrode layer by a patterning process.
1. A manufacturing method of a back channel etching indium gallium zinc oxide thin film transistor (BCE IGZO TFT) device, comprising:
providing a substrate;
depositing a first metal layer on the substrate, and the first metal layer forming a gate and a first electrode layer by a patterning process;
depositing a gate insulating layer on the substrate, the gate, and the first electrode layer;
etching a part of the gate insulating layer on a surface of the first electrode layer;
depositing an active layer on the first electrode layer and the gate insulating layer, and the active later and the first electrode layer in direct contact; and
depositing a second metal layer on the active layer, and the second metal layer forming a source, a drain, and a second electrode layer by a patterning process.
2. The manufacturing method of the BCE IGZO TFT device as claimed in claim 1 , wherein the substrate is a glass substrate or a polyimide flexible substrate, and a thickness of the substrate ranges from 0.01 mm to 10 mm.
3. The manufacturing method of the BCE IGZO TFT device as claimed in claim 1 , wherein the gate insulating layer is a multilayer film structure composed of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or yttrium oxide insulating compound, and a thickness of the gate insulating layer ranges from 10 nm to 1000 nm.
4. The manufacturing method of the BCE IGZO TFT device as claimed in claim 1 , wherein the active layer is IGZO, and a thickness of the active layer ranges from 5 nm to 200 nm.
5. The manufacturing method of the BCE IGZO TFT device as claimed in claim 4 , wherein the gate and the first electrode layer are metal such as Cu, Al, Mo, Nb, Ti or an alloy thereof, or a multilayer film structure composed of the metal, and a thickness of the gate and the first electrode layer is 10 to 1000 nm.
6. The manufacturing method of the BCE IGZO TFT device as claimed in claim 1 , wherein the source, the drain, and the second electrode layer are metal such as Cu, Al, Mo, Nb, Ti or an alloy thereof, or a multilayer film structure composed of the metal, and a thickness of the source, the drain, and the second electrode layer ranges from 10 nm to 1000 nm.
7. A manufacturing method of a back channel etching indium gallium zinc oxide thin film transistor (BCE IGZO TFT) device, comprising:
providing a substrate;
depositing a first metal layer on the substrate, and the first metal layer forming a gate and a first electrode layer by a patterning process;
depositing a gate insulating layer on the substrate, the gate, and the first electrode layer;
etching a part of the gate insulating layer on a surface of the first electrode layer;
disposing an active layer on the first electrode layer and the gate insulating layer without performing etching process, and the active later and the first electrode layer in direct contact; and
depositing a second metal layer on the active layer, and the second metal layer forming a source, a drain, and a second electrode layer by a patterning process.
8. The manufacturing method of the BCE IGZO TFT device as claimed in claim 7 , wherein the substrate is a glass substrate or a polyimide flexible substrate, and a thickness of the substrate ranges from 0.01 mm to 10 mm.
9. The manufacturing method of the BCE IGZO TFT device as claimed in claim 7 , wherein the gate insulating layer is a multilayer film structure composed of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or yttrium oxide insulating compound, and a thickness of the gate insulating layer ranges from 10 nm to 1000 nm.
10. The manufacturing method of the BCE IGZO TFT device as claimed in claim 7 , wherein the active layer is IGZO, and a thickness of the active layer ranges from 5 nm to 200 nm.
11. The manufacturing method of the BCE IGZO TFT device as claimed in claim 7 , wherein the gate and the first electrode layer are metal such as Cu, Al, Mo, Nb, Ti or an alloy thereof, or a multilayer film structure composed of the metal, and a thickness of the gate and the first electrode layer ranges from 10 nm to 1000 nm.
12. The manufacturing method of the BCE IGZO TFT device as claimed in claim 7 , wherein the source, the drain, and the second electrode layer are metal such as Cu, Al, Mo, Nb, Ti or an alloy thereof, or a multilayer film structure composed of the metal, and a thickness of the source, the drain, and the second electrode layer ranges from 10 nm to 1000 nm.
13. A back channel etching indium gallium zinc oxide thin film transistor (BCE IGZO TFT) device, comprising:
a substrate;
a gate disposed on the substrate;
a first electrode layer disposed on the substrate;
a gate insulating layer disposed on the substrate, the gate, and the first electrode layer;
an active layer disposed on the first electrode layer and the gate insulating, and the active layer and the first electrode layer in direct contact;
a source disposed on the active layer;
a drain disposed on the active layer; and
a second electrode layer disposed on the active layer.
14. The BCE IGZO TFT device as claimed in claim 13 , wherein the substrate is a glass substrate or a polyimide flexible substrate, and a thickness of the substrate ranges from 0.01 mm to 10 mm.
15. The BCE IGZO TFT device as claimed in claim 13 , wherein the gate insulating layer is a multilayer film structure composed of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or yttrium oxide insulating compound, and a thickness of the gate insulating layer ranges from 10 nm to 1000 nm.
16. The BCE IGZO TFT device as claimed in claim 13 , wherein the active layer is IGZO, and a thickness of the active layer ranges from 5 nm to 200 nm.
17. The BCE IGZO TFT device as claimed in claim 13 , wherein the gate and the first electrode layer are metal such as Cu, Al, Mo, Nb, Ti or an alloy thereof, or a multilayer film structure composed of the metal, and a thickness of the gate and the first electrode layer ranges from 10 nm to 1000 nm.
18. The BCE IGZO TFT device as claimed in claim 13 , wherein the source, the drain, and the second electrode layer are metal such as Cu, Al, Mo, Nb, Ti or an alloy thereof, or a multilayer film structure composed of the metal, and a thickness of the source, the drain, and the second electrode layer ranges from 10 nm to 1000 nm.