Cointegration of gallium nitride and silicon
The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.
1. A method of forming a semiconductor device, the method comprising:
forming a first wafer comprising, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate a first bonding layer, and a barrier layer structure between the III-V semiconductor layer stack and the first bonding layer, the III-V semiconductor layer stack comprising a GaN-based device layer structure formed on the first substrate and comprising a GaN channel layer;
subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer, the second wafer comprising a second substrate supporting an active device layer, a back-end of line (BEOL) interconnect structure and the second bonding layer; and
subsequent to bonding, thinning the first wafer from a backside thereof, wherein thinning comprises removing at least the first substrate.
2. The method of claim 1 , wherein the III-V semiconductor layer stack comprises a buffer layer structure between the first substrate and the GaN-based device layer structure, and wherein thinning includes removing the buffer layer structure.
3. The method of claim 2 , wherein the III-V semiconductor layer stack comprises one or more etch stop layers between the buffer layer structure and the GaN-based device layer structure.
4. The method of claim 1 , wherein the method further comprises, subsequent to thinning, processing the GaN-based device layer structure to form a transistor device.
5. The method of claim 1 , wherein the barrier layer structure comprises at least an AlGaN layer.
6. The method of claim 1 , wherein the barrier layer structure comprises at least an InAlN layer.
7. The method of claim 1 , wherein the first wafer includes a stress layer structure between the barrier layer structure and the first bonding layer, the stress layer structure comprising a GaN layer.
8. The method of claim 1 , wherein the GaN-based device layer structure comprises a doped source-drain contacting layer in contact with the GaN channel layer, and wherein thinning comprises exposing the doped source-drain contacting layer.
9. The method of claim 1 , wherein the first wafer comprises a metal layer between the GaN-based device layer structure and the first bonding layer, and further comprises an electrically insulating layer between the metal layer and the GaN-based device layer structure.
10. The method of claim 9 , wherein the method further comprises forming, subsequent to bonding, one or more thermal vias connecting to the metal layer.
11. The method of claim 1 , wherein the method further comprises, subsequent to bonding, forming one or more vias connecting to the BEOL interconnect structure.
12. The method of claim 1 , wherein the first substrate comprises a Si substrate having a (111) surface orientation.
13. A semiconductor device, comprising:
a silicon substrate;
an active device layer formed on the substrate;
a back-end-of-line (BEOL) interconnect structure formed on the active device layer;
an N-polar high-electron-mobility transistor (HEMT) bonded via a bonding stack to the interconnect structure and comprising an N-polar GaN channel;
a metal layer between the bonding stack and the HEMT; and
an electrically insulating layer between the metal layer and the HEMT.
14. The semiconductor device of claim 13 , wherein the HEMT is a metal-oxide-semiconductor HEMT.
15. The semiconductor device of claim 13 , wherein a gate of the HEMT is recessed into the N-polar GaN channel.