Method of fabricating semiconductor device
A method of fabricating a semiconductor device includes pattering an upper portion of a substrate to form a first active pattern, the substrate including a semiconductor element having a first lattice constant, performing a selective epitaxial growth process on an upper portion of the first active pattern to form a first source/drain region, doping the first source/drain region with gallium, performing an annealing process on the first source/drain region doped with gallium, and forming a first contact pattern coupled to the first source/drain region. The first source/drain region includes a semiconductor element having a second lattice constant larger than the first lattice constant.
1. A semiconductor device comprising:
a substrate including a first region and a second region;
a first active pattern disposed on the first region of the substrate;
a second active pattern disposed on the first region of the substrate;
a third active pattern disposed on the second region of the substrate;
a fourth active pattern disposed on the second region of the substrate;
a first device isolation disposed on the substrate, and disposed between the first active pattern and the second active pattern;
a second device isolation disposed on the substrate, and disposed between the second active pattern and the third active pattern;
a third device isolation disposed on the substrate, and disposed between the third active pattern and the fourth active pattern;
a first gate electrode disposed on the first active pattern, the second active pattern, the third active pattern, the fourth active pattern, the first device isolation, the second device isolation and the third device isolation;
a second gate electrode disposed on the first active pattern, the second active pattern, the third active pattern, the fourth active pattern, the first device isolation, the second device isolation and the third device isolation;
a first source/drain disposed on the first active pattern, and disposed between the first gate electrode and the second gate electrode;
a second source/drain disposed on the second active pattern, and disposed between the first gate electrode and the second gate electrode;
a third source/drain disposed on the third active pattern, and disposed between the first gate electrode and the second gate electrode; and
a fourth source/drain disposed on the fourth active pattern, and disposed between the first gate electrode and the second gate electrode,
wherein each of the first source/drain and the second source/drain includes gallium (Ga), and each of the third source/drain and the fourth source/drain does not include gallium (Ga).
2. The semiconductor device of claim 1 ,
wherein the first region is a PMOSFET region, and
the second region is an NMOSFET region.
3. The semiconductor device of claim 1 ,
wherein the first source/drain includes:
a first semiconductor pattern;
a second semiconductor pattern disposed on the first semiconductor pattern;
a third semiconductor pattern disposed on the second semiconductor pattern, and including gallium (Ga); and
a fourth semiconductor pattern disposed on the third semiconductor pattern.
4. The semiconductor device of claim 3 ,
wherein the first semiconductor pattern of the first source/drain is U-shaped.
5. The semiconductor device of claim 1 ,
wherein a shape of the first source/drain is different from a shape of the third source/drain.
6. The semiconductor device of claim 1 ,
wherein a bottom portion of each of the first source/drain and the second source/drain is angular, and
a bottom portion of each of the third source/drain and the fourth source/drain is rounded.
7. The semiconductor device of claim 1 ,
wherein a distance between the first source/drain and the second source/drain is different from a distance between the third source/drain and the fourth source/drain.
8. The semiconductor device of claim 1 ,
wherein a width of the first device isolation is different from a width of the second device isolation.
9. A semiconductor device comprising:
a substrate including a first region and a second region;
a first active pattern disposed on the first region of the substrate;
a second active pattern disposed on the first region of the substrate;
a third active pattern disposed on the second region of the substrate;
a fourth active pattern disposed on the second region of the substrate;
a first device isolation disposed on the substrate, and disposed between the first active pattern and the second active pattern;
a second device isolation disposed on the substrate, and disposed between the second active pattern and the third active pattern;
a third device isolation disposed on the substrate, and disposed between the third active pattern and the fourth active pattern;
a first gate electrode disposed on the first active pattern, the second active pattern, the third active pattern, the fourth active pattern, the first device isolation, the second device isolation and the third device isolation;
a second gate electrode disposed on the first active pattern, the second active pattern, the third active pattern, the fourth active pattern, the first device isolation, the second device isolation and the third device isolation;
a first source/drain disposed on the first active pattern, and disposed between the first gate electrode and the second gate electrode;
a second source/drain disposed on the second active pattern, and disposed between the first gate electrode and the second gate electrode;
a third source/drain disposed on the third active pattern, and disposed between the first gate electrode and the second gate electrode; and
a fourth source/drain disposed on the fourth active pattern, and disposed between the first gate electrode and the second gate electrode,
wherein the first source/drain includes
a first semiconductor pattern,
a second semiconductor pattern disposed on the first semiconductor pattern,
a third semiconductor pattern disposed on the second semiconductor pattern, and
a fourth semiconductor pattern disposed on the third semiconductor pattern, and
the third semiconductor pattern of the first source/drain includes gallium (Ga).
10. The semiconductor device of claim 9 ,
wherein the second source/drain includes gallium, and
each of the third source/drain and the fourth source/drain does not include gallium (Ga).
11. The semiconductor device of claim 9 ,
wherein a shape of the first source/drain is different from a shape of the third source/drain.
12. The semiconductor device of claim 9 ,
wherein a bottom portion of the first source/drain is angular, and
a bottom portion of the third source/drain is rounded.
13. The semiconductor device of claim 9 , further comprising:
a first contact disposed on the first source/drain and the second source/drain; and
a second contact disposed on the third source/drain and the fourth source/drain.
14. The semiconductor device of claim 9 ,
wherein the first region is a PMOSFET region, and
the second region is an NMOSFET region.
15. The semiconductor device of claim 9 ,
wherein a distance between the first source/drain and the second source/drain is less than a distance between the third source/drain and the fourth source/drain.
16. A semiconductor device comprising:
a substrate including a PMOSFET region and an NMOSFET region;
a first fin disposed on the PMOSFET region of the substrate;
a second fin disposed on the PMOSFET region of the substrate;
a third fin disposed on the NMOSFET region of the substrate;
a fourth fin disposed on the NMOSFET region of the substrate;
a first device isolation disposed on the substrate, and disposed between the first fin and the second fin;
a second device isolation disposed on the substrate, and disposed between the second fin and the third fin;
a third device isolation disposed on the substrate, and disposed between the third fin and the fourth fin;
a first gate electrode disposed on the first fin, the second fin, the third fin, the fourth fin, the first device isolation, the second device isolation and the third device isolation;
a second gate electrode disposed on the first fin, the second fin, the third fin, the fourth fin, the first device isolation, the second device isolation and the third device isolation;
a first source/drain disposed on the first fin, and disposed between the first gate electrode and the second gate electrode;
a second source/drain disposed on the second fin, and disposed between the first gate electrode and the second gate electrode;
a third source/drain disposed on the third fin, and disposed between the first gate electrode and the second gate electrode; and
a fourth source/drain disposed on the fourth fin, and disposed between the first gate electrode and the second gate electrode,
wherein the first source/drain includes gallium (Ga),
a shape of the first source/drain is different from a shape of the third source/drain, and
a width of the first device isolation is different from a width of the second device isolation.
17. The semiconductor device of claim 16 ,
wherein the third source/drain does not include gallium (Ga).
18. The semiconductor device of claim 16 ,
wherein the first source/drain includes
a first semiconductor pattern,
a second semiconductor pattern disposed on the first semiconductor pattern,
a third semiconductor pattern disposed on the second semiconductor pattern and including gallium (Ga), and
a fourth semiconductor pattern disposed on the third semiconductor pattern, and
the third source/drain is formed as one pattern.
19. The semiconductor device of claim 16 ,
wherein a distance between the first source/drain and the second source/drain is different from a distance between the third source/drain and the fourth source/drain.
20. The semiconductor device of claim 16 ,
wherein a bottom portion of the first source/drain is angular, and a bottom portion of the third source/drain is rounded.