IP Library › Granted Patent US 11,322,523
Granted Patent B2
US 11,322,523 · App. 16/627,097 · Granted May 3, 2022

Active matrix substrate, display device, and method of manufacturing active matrix substrate

Inventors: Keiichi Ina (Sakai, JP); Yasuyoshi Kaise (Sakai, JP)
Assignee: SHARP KABUSHIKI KAISHA
H01L27/124G02F1/1368G02F1/136286G04G17/02H01L27/1259H01L29/404G02F1/136218G02F2201/121G02F2201/123G02F2201/56G04B19/04
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Quick Facts
Patent No.
US 11,322,523
App. No.
16/627,097
Granted
May 3, 2022
Kind
B2
Abstract

To reduce a reduction in the quality of a displayed image in portions corresponding to source lines including detour portions in a display area. Gate lines ( 20 ) and source lines ( 30 ), which intersect with each other, extend on an insulating substrate ( 1 ) so as to detour an opening area (A 1 ). Separated portions ( 24 ) are provided as lower shielding electrodes ( 23 ) in an inner non-display area (A 2 ) so as to be overlapped with source detour portions ( 31 ) of the source lines ( 30 ) in a plan view.

Claims (33)

1. An active matrix substrate comprising:

a substrate on which an opening area, an inner non-display area at an outer side of the opening area, and a display area at an outer side of the inner non-display area are set;

a plurality of gate lines and a plurality of source lines intersecting with the plurality of gate lines arranged in an array, at least two of the plurality of gate lines including a gate arc-shaped portion that bypasses the opening area on opposite row sides and at least two of the plurality of source lines including a source arc-shaped portion that bypasses the opening area on opposite column sides;

a plurality of pixel electrodes provided in the display area on the substrate and surrounded by the plurality of gate lines and the plurality of source lines only in the display area; and

a shielding electrode provided in the inner non-display area on the substrate and overlapped with the source arc-shaped portion in a plan view, wherein:

a substantially circular shape in the plan view is formed by two of the gate arc-shaped portions and two of the source arc-shaped portions, the substantially circular shape being aligned along an outline of the opening area in the plan view, and

in the non-display area, the gate arc-shaped portion and the source arc-shaped portion are crossing each other at an angle not equal to a right angle.

2. The active matrix substrate according to claim 1 , wherein the shielding electrode is provided closer to the substrate side than the overlapping source arc-shaped portion.

3. The active matrix substrate according to claim 2 ,

wherein a first conductive layer comprising the plurality of gate lines formed thereon is provided and laminated closer to the substrate side than a second conductive layer comprising the plurality of source lines formed thereon, and

wherein the shielding electrode is formed of the first conductive layer.

4. The active matrix substrate according to claim 3 , wherein the shielding electrode is connected to the gate arc-shaped portion.

5. The active matrix substrate according to claim 1 , wherein the shielding electrode is provided at a side of the substrate farther than the overlapping source arc-shaped portion from the substrate.

6. The active matrix substrate according to claim 5 ,

wherein a third conductive layer comprising the pixel electrodes is provided and laminated at a side of the substrate farther than the second conductive layer from the substrate, wherein

the plurality of source lines is formed on the second conductive layer, and

the shielding electrode is formed of the third conductive layer.

7. The active matrix substrate according to claim 5 , further comprising:

a common electrode,

wherein a fourth conductive layer comprising the common electrode is provided and laminated at a side of the substrate farther than the second conductive layer from the substrate,

wherein the plurality of source lines is formed on the second conductive layer, and the shielding electrode is formed of the fourth conductive layer.

8. The active matrix substrate according to claim 1 , wherein the shielding electrode is connected to electrodes or lines having constant potential.

9. The active matrix substrate according to claim 1 , wherein only an insulating layer is sandwiched between the shielding electrode and the overlapping source arc-shaped portion.

10. The active matrix substrate according to claim 1 , wherein a width of the shielding electrode is greater than a width of the overlapping source arc-shaped portion.

11. The active matrix substrate according to claim 1 , wherein the shielding electrode is provided along the overlapping source arc-shaped portion.

12. A display device comprising the active matrix substrate according to claim 1 .

13. A method of manufacturing an active matrix substrate, the method comprising:

setting an opening area, an inner non-display area at an outer side of the opening area, and a display area at an outer side of the inner non-display area on a substrate;

providing a plurality of gate lines and source lines on the substrate, the gate lines intersecting with the source lines forming in an array; at least two of the plurality of gate lines including a gate arc-shaped portion that bypasses the opening area on opposite row sides; at least two of the plurality of source lines including a source arc-shaped portion that bypasses the opening area on opposite column sides;

providing a plurality of pixel electrodes in the display area on the substrate and surrounded by the plurality of gate lines and the plurality of source lines only in the display area;

providing a shielding electrode in the inner non-display area on the substrate and overlapped with the source arc-shaped portion in a plan view; and

forming a substantially circular shape aligned along an outline of the opening area in the plan view that is formed by two of the gate arc-shaped portions and two of the source arc-shaped portions, wherein

in the non-display area, the gate arc-shaped portion and the source arc-shaped portion are crossing each other at an angle not equal to a right angle.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2019
From: INA, KEIICHI; KAISE, YASUYOSHI
To: SHARP KABUSHIKI KAISHA
Reel/Frame 051377/0750 →
Priority Claims (1)
JP JP2017-132280 · Jul 5, 2017 · national
Continuity (1)
Related Publication 20200168633A1 · May 28, 2020