Semiconductor device with first and second data structures
A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.
1. A vertical semiconductor device, comprising:
a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate;
a first data storage structure contacting a first sidewall of the channel;
a second data storage structure on a second sidewall of the channel; and
gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.
2. The vertical semiconductor device of claim 1 , wherein the first data storage structure includes a variable resistance material.
3. The vertical semiconductor device of claim wherein the first data storage structure includes STO (SrTiO3), BTO (BaTiO3), PCMO (Pr1-XCaXMnO3), zirconium oxide, hafnium oxide, hafhium aluminum oxide, hafnium silicon oxide, aluminum oxide, titanium oxide or tantalum oxide.
4. The vertical semiconductor device of claim 1 , wherein the first data storage structure includes a GeSe material or a phase change material including germanium (Ge), antimony (Sb), or tellurium (Te).
5. The vertical semiconductor device of claim 1 , wherein the second data storage structure includes a tunnel insulation layer, a charge storage layer, and a blocking layer.
6. The vertical semiconductor device of claim 5 , wherein the charge storage layer is a floating, layer including silicon.
7. The vertical semiconductor device of claim 5 , wherein the charge storage layer is a charge trap layer including a silicon nitride or a metal nitride.
8. The vertical semiconductor device of claim 1 , wherein the first data storage structure covers the first sidewall of the channel.
9. The vertical semiconductor device of claim 1 , wherein a plurality of first data storage structures are spaced apart from each other in the first direction, and the first data storage structures face each other in a horizontal direction with respect to the upper surface of the substrate.
10. The vertical semiconductor device of claim 1 , wherein data are stored in the first data storage structure and the second data storage structure, respectively, by electric fields in different directions.
11. The vertical semiconductor device of claim 1 , wherein first data is stored in the first data storage structure by electric fields in a direction substantially parallel to the first sidewall of the channel, and second data is stored in the second data storage structure by electric fields in a direction substantially perpendicular to the first sidewall of the channel.
12. The vertical semiconductor device of claim 1 , wherein the second data storage structure contacts a portion of the surface of the gate patterns.
13. The vertical semiconductor device of claim 12 , wherein the second data storage structure surrounds the surface of the gate patterns.
14. A vertical semiconductor device, comprising:
gate patterns stacked on a substrate, wherein the gate patterns are spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate;
a channel passing through the gate patterns, wherein the channel is electrically connected to the substrate, and the channel has a cylindrical shape;
a first data storage structure contacting a first sidewall of the channel; and
a second data storage structure on a second sidewall of the channel opposite the first sidewall, wherein the second data storage structure contacts the channel.
15. The vertical semiconductor device of claim 14 , wherein the first data storage structure includes a variable resistance material.
16. The vertical semiconductor device of claim 14 , wherein the second data storage structure includes a tunnel insulation layer, a charge storage layer, and a blocking layer.
17. The vertical semiconductor device of claim 14 , wherein first data is stored in the first data storage structure by electric fields in a direction substantially parallel to the first sidewall of the channel, and second data is stored in the second data storage structure by electric fields in a direction substantially perpendicular to the first sidewall of the channel.
18. A vertical semiconductor device, comprising:
a first gate pattern and a second gate pattern arranged in a vertical direction on a substrate, wherein an insulation layer is disposed between the first gate pattern and the second gate pattern;
a channel layer disposed on the substrate;
a first data storage element disposed on a first side of the Channel layer; and
a second data storage element disposed on a second side of the channel layer, wherein the second data storage element is disposed between the second side of the channel layer and the first gate pattern.
19. The vertical semiconductor device of claim 18 , wherein the channel layer directly contacts the first data storage element and the second data storage element.
20. The vertical semiconductor device of claim 18 , wherein the first data storage element and the second data storage element include different materials from each other.